10284b52eSThara Gopinath# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 20284b52eSThara Gopinath# Copyright 2021 Linaro Ltd. 30284b52eSThara Gopinath%YAML 1.2 40284b52eSThara Gopinath--- 50284b52eSThara Gopinath$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml# 60284b52eSThara Gopinath$schema: http://devicetree.org/meta-schemas/core.yaml# 70284b52eSThara Gopinath 80284b52eSThara Gopinathtitle: Qualcomm Limits Management Hardware(LMh) 90284b52eSThara Gopinath 100284b52eSThara Gopinathmaintainers: 110284b52eSThara Gopinath - Thara Gopinath <thara.gopinath@linaro.org> 120284b52eSThara Gopinath 130284b52eSThara Gopinathdescription: 140284b52eSThara Gopinath Limits Management Hardware(LMh) is a hardware infrastructure on some 150284b52eSThara Gopinath Qualcomm SoCs that can enforce temperature and current limits as 160284b52eSThara Gopinath programmed by software for certain IPs like CPU. 170284b52eSThara Gopinath 180284b52eSThara Gopinathproperties: 190284b52eSThara Gopinath compatible: 200284b52eSThara Gopinath enum: 210284b52eSThara Gopinath - qcom,sdm845-lmh 22*1f43fad1SThara Gopinath - qcom,sm8150-lmh 230284b52eSThara Gopinath 240284b52eSThara Gopinath reg: 250284b52eSThara Gopinath items: 260284b52eSThara Gopinath - description: core registers 270284b52eSThara Gopinath 280284b52eSThara Gopinath interrupts: 290284b52eSThara Gopinath maxItems: 1 300284b52eSThara Gopinath 310284b52eSThara Gopinath '#interrupt-cells': 320284b52eSThara Gopinath const: 1 330284b52eSThara Gopinath 340284b52eSThara Gopinath interrupt-controller: true 350284b52eSThara Gopinath 360284b52eSThara Gopinath cpus: 370284b52eSThara Gopinath description: 380284b52eSThara Gopinath phandle of the first cpu in the LMh cluster 390284b52eSThara Gopinath $ref: /schemas/types.yaml#/definitions/phandle 400284b52eSThara Gopinath 410284b52eSThara Gopinath qcom,lmh-temp-arm-millicelsius: 420284b52eSThara Gopinath description: 430284b52eSThara Gopinath An integer expressing temperature threshold at which the LMh thermal 440284b52eSThara Gopinath FSM is engaged. 450284b52eSThara Gopinath 460284b52eSThara Gopinath qcom,lmh-temp-low-millicelsius: 470284b52eSThara Gopinath description: 480284b52eSThara Gopinath An integer expressing temperature threshold at which the state machine 490284b52eSThara Gopinath will attempt to remove frequency throttling. 500284b52eSThara Gopinath 510284b52eSThara Gopinath qcom,lmh-temp-high-millicelsius: 520284b52eSThara Gopinath description: 530284b52eSThara Gopinath An integer expressing temperature threshold at which the state machine 540284b52eSThara Gopinath will attempt to throttle the frequency. 550284b52eSThara Gopinath 560284b52eSThara Gopinathrequired: 570284b52eSThara Gopinath - compatible 580284b52eSThara Gopinath - reg 590284b52eSThara Gopinath - interrupts 600284b52eSThara Gopinath - '#interrupt-cells' 610284b52eSThara Gopinath - interrupt-controller 620284b52eSThara Gopinath - cpus 630284b52eSThara Gopinath - qcom,lmh-temp-arm-millicelsius 640284b52eSThara Gopinath - qcom,lmh-temp-low-millicelsius 650284b52eSThara Gopinath - qcom,lmh-temp-high-millicelsius 660284b52eSThara Gopinath 670284b52eSThara GopinathadditionalProperties: false 680284b52eSThara Gopinath 690284b52eSThara Gopinathexamples: 700284b52eSThara Gopinath - | 710284b52eSThara Gopinath #include <dt-bindings/interrupt-controller/arm-gic.h> 720284b52eSThara Gopinath 730284b52eSThara Gopinath lmh@17d70800 { 740284b52eSThara Gopinath compatible = "qcom,sdm845-lmh"; 750284b52eSThara Gopinath reg = <0x17d70800 0x400>; 760284b52eSThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 770284b52eSThara Gopinath cpus = <&CPU4>; 780284b52eSThara Gopinath qcom,lmh-temp-arm-millicelsius = <65000>; 790284b52eSThara Gopinath qcom,lmh-temp-low-millicelsius = <94500>; 800284b52eSThara Gopinath qcom,lmh-temp-high-millicelsius = <95000>; 810284b52eSThara Gopinath interrupt-controller; 820284b52eSThara Gopinath #interrupt-cells = <1>; 830284b52eSThara Gopinath }; 84