1* Mediatek Thermal
2
3This describes the device tree binding for the Mediatek thermal controller
4which measures the on-SoC temperatures. This device does not have its own ADC,
5instead it directly controls the AUXADC via AHB bus accesses. For this reason
6this device needs phandles to the AUXADC. Also it controls a mux in the
7apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
8is also needed.
9
10Required properties:
11- compatible:
12  - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
13  - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
14  - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
15  - "mediatek,mt7622-thermal" : For MT7622 SoC
16  - "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
17  - "mediatek,mt7986-thermal" : For MT7986 SoC
18  - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
19  - "mediatek,mt8365-thermal" : For MT8365 family of SoCs
20  - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
21- reg: Address range of the thermal controller
22- interrupts: IRQ for the thermal controller
23- clocks, clock-names: Clocks needed for the thermal controller. required
24                       clocks are:
25		       "therm":	 Main clock needed for register access
26		       "auxadc": The AUXADC clock
27- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
28- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
29- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
30
31Optional properties:
32- resets: Reference to the reset controller controlling the thermal controller.
33- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
34               unspecified default values shall be used.
35- nvmem-cell-names: Should be "calibration-data"
36
37Example:
38
39	thermal: thermal@1100b000 {
40		#thermal-sensor-cells = <1>;
41		compatible = "mediatek,mt8173-thermal";
42		reg = <0 0x1100b000 0 0x1000>;
43		interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
44		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
45		clock-names = "therm", "auxadc";
46		resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
47		reset-names = "therm";
48		mediatek,auxadc = <&auxadc>;
49		mediatek,apmixedsys = <&apmixedsys>;
50		nvmem-cells = <&thermal_calibration_data>;
51		nvmem-cell-names = "calibration-data";
52	};
53