1*498e2f7aSBalsam CHIHI# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*498e2f7aSBalsam CHIHI%YAML 1.2 3*498e2f7aSBalsam CHIHI--- 4*498e2f7aSBalsam CHIHI$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# 5*498e2f7aSBalsam CHIHI$schema: http://devicetree.org/meta-schemas/core.yaml# 6*498e2f7aSBalsam CHIHI 7*498e2f7aSBalsam CHIHItitle: MediaTek SoC Low Voltage Thermal Sensor (LVTS) 8*498e2f7aSBalsam CHIHI 9*498e2f7aSBalsam CHIHImaintainers: 10*498e2f7aSBalsam CHIHI - Balsam CHIHI <bchihi@baylibre.com> 11*498e2f7aSBalsam CHIHI 12*498e2f7aSBalsam CHIHIdescription: | 13*498e2f7aSBalsam CHIHI LVTS is a thermal management architecture composed of three subsystems, 14*498e2f7aSBalsam CHIHI a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU), 15*498e2f7aSBalsam CHIHI a Converter - Low Voltage Thermal Sensor converter (LVTS), and 16*498e2f7aSBalsam CHIHI a Digital controller (LVTS_CTRL). 17*498e2f7aSBalsam CHIHI 18*498e2f7aSBalsam CHIHIproperties: 19*498e2f7aSBalsam CHIHI compatible: 20*498e2f7aSBalsam CHIHI enum: 21*498e2f7aSBalsam CHIHI - mediatek,mt8192-lvts-ap 22*498e2f7aSBalsam CHIHI - mediatek,mt8192-lvts-mcu 23*498e2f7aSBalsam CHIHI - mediatek,mt8195-lvts-ap 24*498e2f7aSBalsam CHIHI - mediatek,mt8195-lvts-mcu 25*498e2f7aSBalsam CHIHI 26*498e2f7aSBalsam CHIHI reg: 27*498e2f7aSBalsam CHIHI maxItems: 1 28*498e2f7aSBalsam CHIHI 29*498e2f7aSBalsam CHIHI interrupts: 30*498e2f7aSBalsam CHIHI maxItems: 1 31*498e2f7aSBalsam CHIHI 32*498e2f7aSBalsam CHIHI clocks: 33*498e2f7aSBalsam CHIHI maxItems: 1 34*498e2f7aSBalsam CHIHI 35*498e2f7aSBalsam CHIHI resets: 36*498e2f7aSBalsam CHIHI maxItems: 1 37*498e2f7aSBalsam CHIHI description: LVTS reset for clearing temporary data on AP/MCU. 38*498e2f7aSBalsam CHIHI 39*498e2f7aSBalsam CHIHI nvmem-cells: 40*498e2f7aSBalsam CHIHI minItems: 1 41*498e2f7aSBalsam CHIHI items: 42*498e2f7aSBalsam CHIHI - description: Calibration eFuse data 1 for LVTS 43*498e2f7aSBalsam CHIHI - description: Calibration eFuse data 2 for LVTS 44*498e2f7aSBalsam CHIHI 45*498e2f7aSBalsam CHIHI nvmem-cell-names: 46*498e2f7aSBalsam CHIHI minItems: 1 47*498e2f7aSBalsam CHIHI items: 48*498e2f7aSBalsam CHIHI - const: lvts-calib-data-1 49*498e2f7aSBalsam CHIHI - const: lvts-calib-data-2 50*498e2f7aSBalsam CHIHI 51*498e2f7aSBalsam CHIHI "#thermal-sensor-cells": 52*498e2f7aSBalsam CHIHI const: 1 53*498e2f7aSBalsam CHIHI 54*498e2f7aSBalsam CHIHIallOf: 55*498e2f7aSBalsam CHIHI - $ref: thermal-sensor.yaml# 56*498e2f7aSBalsam CHIHI 57*498e2f7aSBalsam CHIHI - if: 58*498e2f7aSBalsam CHIHI properties: 59*498e2f7aSBalsam CHIHI compatible: 60*498e2f7aSBalsam CHIHI contains: 61*498e2f7aSBalsam CHIHI enum: 62*498e2f7aSBalsam CHIHI - mediatek,mt8192-lvts-ap 63*498e2f7aSBalsam CHIHI - mediatek,mt8192-lvts-mcu 64*498e2f7aSBalsam CHIHI then: 65*498e2f7aSBalsam CHIHI properties: 66*498e2f7aSBalsam CHIHI nvmem-cells: 67*498e2f7aSBalsam CHIHI maxItems: 1 68*498e2f7aSBalsam CHIHI 69*498e2f7aSBalsam CHIHI nvmem-cell-names: 70*498e2f7aSBalsam CHIHI maxItems: 1 71*498e2f7aSBalsam CHIHI 72*498e2f7aSBalsam CHIHI - if: 73*498e2f7aSBalsam CHIHI properties: 74*498e2f7aSBalsam CHIHI compatible: 75*498e2f7aSBalsam CHIHI contains: 76*498e2f7aSBalsam CHIHI enum: 77*498e2f7aSBalsam CHIHI - mediatek,mt8195-lvts-ap 78*498e2f7aSBalsam CHIHI - mediatek,mt8195-lvts-mcu 79*498e2f7aSBalsam CHIHI then: 80*498e2f7aSBalsam CHIHI properties: 81*498e2f7aSBalsam CHIHI nvmem-cells: 82*498e2f7aSBalsam CHIHI minItems: 2 83*498e2f7aSBalsam CHIHI 84*498e2f7aSBalsam CHIHI nvmem-cell-names: 85*498e2f7aSBalsam CHIHI minItems: 2 86*498e2f7aSBalsam CHIHI 87*498e2f7aSBalsam CHIHIrequired: 88*498e2f7aSBalsam CHIHI - compatible 89*498e2f7aSBalsam CHIHI - reg 90*498e2f7aSBalsam CHIHI - interrupts 91*498e2f7aSBalsam CHIHI - clocks 92*498e2f7aSBalsam CHIHI - resets 93*498e2f7aSBalsam CHIHI - nvmem-cells 94*498e2f7aSBalsam CHIHI - nvmem-cell-names 95*498e2f7aSBalsam CHIHI - "#thermal-sensor-cells" 96*498e2f7aSBalsam CHIHI 97*498e2f7aSBalsam CHIHIadditionalProperties: false 98*498e2f7aSBalsam CHIHI 99*498e2f7aSBalsam CHIHIexamples: 100*498e2f7aSBalsam CHIHI - | 101*498e2f7aSBalsam CHIHI #include <dt-bindings/interrupt-controller/arm-gic.h> 102*498e2f7aSBalsam CHIHI #include <dt-bindings/clock/mt8195-clk.h> 103*498e2f7aSBalsam CHIHI #include <dt-bindings/reset/mt8195-resets.h> 104*498e2f7aSBalsam CHIHI #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 105*498e2f7aSBalsam CHIHI 106*498e2f7aSBalsam CHIHI soc { 107*498e2f7aSBalsam CHIHI #address-cells = <2>; 108*498e2f7aSBalsam CHIHI #size-cells = <2>; 109*498e2f7aSBalsam CHIHI 110*498e2f7aSBalsam CHIHI lvts_mcu: thermal-sensor@11278000 { 111*498e2f7aSBalsam CHIHI compatible = "mediatek,mt8195-lvts-mcu"; 112*498e2f7aSBalsam CHIHI reg = <0 0x11278000 0 0x1000>; 113*498e2f7aSBalsam CHIHI interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 114*498e2f7aSBalsam CHIHI clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 115*498e2f7aSBalsam CHIHI resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 116*498e2f7aSBalsam CHIHI nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 117*498e2f7aSBalsam CHIHI nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 118*498e2f7aSBalsam CHIHI #thermal-sensor-cells = <1>; 119*498e2f7aSBalsam CHIHI }; 120*498e2f7aSBalsam CHIHI }; 121*498e2f7aSBalsam CHIHI 122*498e2f7aSBalsam CHIHI thermal_zones: thermal-zones { 123*498e2f7aSBalsam CHIHI cpu0-thermal { 124*498e2f7aSBalsam CHIHI polling-delay = <1000>; 125*498e2f7aSBalsam CHIHI polling-delay-passive = <250>; 126*498e2f7aSBalsam CHIHI thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 127*498e2f7aSBalsam CHIHI 128*498e2f7aSBalsam CHIHI trips { 129*498e2f7aSBalsam CHIHI cpu0_alert: trip-alert { 130*498e2f7aSBalsam CHIHI temperature = <85000>; 131*498e2f7aSBalsam CHIHI hysteresis = <2000>; 132*498e2f7aSBalsam CHIHI type = "passive"; 133*498e2f7aSBalsam CHIHI }; 134*498e2f7aSBalsam CHIHI 135*498e2f7aSBalsam CHIHI cpu0_crit: trip-crit { 136*498e2f7aSBalsam CHIHI temperature = <100000>; 137*498e2f7aSBalsam CHIHI hysteresis = <2000>; 138*498e2f7aSBalsam CHIHI type = "critical"; 139*498e2f7aSBalsam CHIHI }; 140*498e2f7aSBalsam CHIHI }; 141*498e2f7aSBalsam CHIHI }; 142*498e2f7aSBalsam CHIHI }; 143