1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - atmel,sama5d2-securam
32        - rockchip,rk3288-pmu-sram
33
34  reg:
35    maxItems: 1
36
37  clocks:
38    maxItems: 1
39    description:
40      A list of phandle and clock specifier pair that controls the single
41      SRAM clock.
42
43  "#address-cells":
44    const: 1
45
46  "#size-cells":
47    const: 1
48
49  ranges:
50    maxItems: 1
51    description:
52      Should translate from local addresses within the sram to bus addresses.
53
54  no-memory-wc:
55    description:
56      The flag indicating, that SRAM memory region has not to be remapped
57      as write combining. WC is used by default.
58    type: boolean
59
60patternProperties:
61  "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
62    type: object
63    description:
64      Each child of the sram node specifies a region of reserved memory.
65    properties:
66      compatible:
67        description:
68          Should contain a vendor specific string in the form
69          <vendor>,[<device>-]<usage>
70        contains:
71          enum:
72            - allwinner,sun4i-a10-sram-a3-a4
73            - allwinner,sun4i-a10-sram-c1
74            - allwinner,sun4i-a10-sram-d
75            - allwinner,sun9i-a80-smp-sram
76            - allwinner,sun50i-a64-sram-c
77            - amlogic,meson8-ao-arc-sram
78            - amlogic,meson8b-ao-arc-sram
79            - amlogic,meson8-smp-sram
80            - amlogic,meson8b-smp-sram
81            - amlogic,meson-gxbb-scp-shmem
82            - amlogic,meson-axg-scp-shmem
83            - renesas,smp-sram
84            - rockchip,rk3066-smp-sram
85            - samsung,exynos4210-sysram
86            - samsung,exynos4210-sysram-ns
87            - socionext,milbeaut-smp-sram
88
89      reg:
90        description:
91          IO mem address range, relative to the SRAM range.
92        maxItems: 1
93
94      pool:
95        description:
96          Indicates that the particular reserved SRAM area is addressable
97          and in use by another device or devices.
98        type: boolean
99
100      export:
101        description:
102          Indicates that the reserved SRAM area may be accessed outside
103          of the kernel, e.g. by bootloader or userspace.
104        type: boolean
105
106      protect-exec:
107        description: |
108          Same as 'pool' above but with the additional constraint that code
109          will be run from the region and that the memory is maintained as
110          read-only, executable during code execution. NOTE: This region must
111          be page aligned on start and end in order to properly allow
112          manipulation of the page attributes.
113        type: boolean
114
115      label:
116        description:
117          The name for the reserved partition, if omitted, the label is taken
118          from the node name excluding the unit address.
119
120    required:
121      - reg
122
123    additionalProperties: false
124
125required:
126  - compatible
127  - reg
128
129if:
130  properties:
131    compatible:
132      contains:
133        const: rockchip,rk3288-pmu-sram
134
135else:
136  required:
137    - "#address-cells"
138    - "#size-cells"
139    - ranges
140
141additionalProperties: false
142
143examples:
144  - |
145    sram@5c000000 {
146        compatible = "mmio-sram";
147        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
148
149        #address-cells = <1>;
150        #size-cells = <1>;
151        ranges = <0 0x5c000000 0x40000>;
152
153        smp-sram@100 {
154            reg = <0x100 0x50>;
155        };
156
157        device-sram@1000 {
158            reg = <0x1000 0x1000>;
159            pool;
160        };
161
162        exported-sram@20000 {
163            reg = <0x20000 0x20000>;
164            export;
165        };
166    };
167
168  - |
169    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
170    // of the secondary cores. Once the core gets powered up it executes the
171    // code that is residing at some specific location of the SYSRAM.
172    //
173    // Therefore reserved section sub-nodes have to be added to the mmio-sram
174    // declaration. These nodes are of two types depending upon secure or
175    // non-secure execution environment.
176    sram@2020000 {
177        compatible = "mmio-sram";
178        reg = <0x02020000 0x54000>;
179        #address-cells = <1>;
180        #size-cells = <1>;
181        ranges = <0 0x02020000 0x54000>;
182
183        smp-sram@0 {
184            compatible = "samsung,exynos4210-sysram";
185            reg = <0x0 0x1000>;
186        };
187
188        smp-sram@53000 {
189            compatible = "samsung,exynos4210-sysram-ns";
190            reg = <0x53000 0x1000>;
191        };
192    };
193
194  - |
195    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
196    // Once the core gets powered up it executes the code that is residing at a
197    // specific location.
198    //
199    // Therefore a reserved section sub-node has to be added to the mmio-sram
200    // declaration.
201    sram@d9000000 {
202        compatible = "mmio-sram";
203        reg = <0xd9000000 0x20000>;
204        #address-cells = <1>;
205        #size-cells = <1>;
206        ranges = <0 0xd9000000 0x20000>;
207
208        smp-sram@1ff80 {
209            compatible = "amlogic,meson8b-smp-sram";
210            reg = <0x1ff80 0x8>;
211        };
212    };
213
214  - |
215    sram@e63c0000 {
216        compatible = "mmio-sram";
217        reg = <0xe63c0000 0x1000>;
218        #address-cells = <1>;
219        #size-cells = <1>;
220        ranges = <0 0xe63c0000 0x1000>;
221
222        smp-sram@0 {
223            compatible = "renesas,smp-sram";
224            reg = <0 0x10>;
225        };
226    };
227
228  - |
229    sram@10080000 {
230        compatible = "mmio-sram";
231        reg = <0x10080000 0x10000>;
232        #address-cells = <1>;
233        #size-cells = <1>;
234        ranges;
235
236        smp-sram@10080000 {
237            compatible = "rockchip,rk3066-smp-sram";
238            reg = <0x10080000 0x50>;
239        };
240    };
241
242  - |
243    // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
244    // resume from maskrom(the 1st level loader). This is a common use of
245    // the "pmu-sram" because it keeps power even in low power states
246    // in the system.
247    sram@ff720000 {
248      compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
249      reg = <0xff720000 0x1000>;
250    };
251
252  - |
253    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
254    // primary core (cpu0). Once the core gets powered up it checks if a magic
255    // value is set at a specific location. If it is then the BROM will jump
256    // to the software entry address, instead of executing a standard boot.
257    //
258    // Also there are no "secure-only" properties. The implementation should
259    // check if this SRAM is usable first.
260    sram@20000 {
261        // 256 KiB secure SRAM at 0x20000
262        compatible = "mmio-sram";
263        reg = <0x00020000 0x40000>;
264        #address-cells = <1>;
265        #size-cells = <1>;
266        ranges = <0 0x00020000 0x40000>;
267
268        smp-sram@1000 {
269            // This is checked by BROM to determine if
270            // cpu0 should jump to SMP entry vector
271            compatible = "allwinner,sun9i-a80-smp-sram";
272            reg = <0x1000 0x8>;
273        };
274    };
275
276  - |
277    sram@0 {
278        compatible = "mmio-sram";
279        reg = <0x0 0x10000>;
280        #address-cells = <1>;
281        #size-cells = <1>;
282        ranges = <0 0x0 0x10000>;
283
284        smp-sram@f100 {
285            compatible = "socionext,milbeaut-smp-sram";
286            reg = <0xf100 0x20>;
287        };
288    };
289