1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - atmel,sama5d2-securam
32
33  reg:
34    maxItems: 1
35
36  clocks:
37    description:
38      A list of phandle and clock specifier pair that controls the single
39      SRAM clock.
40
41  "#address-cells":
42    const: 1
43
44  "#size-cells":
45    const: 1
46
47  ranges:
48    description:
49      Should translate from local addresses within the sram to bus addresses.
50
51  no-memory-wc:
52    description:
53      The flag indicating, that SRAM memory region has not to be remapped
54      as write combining. WC is used by default.
55    type: boolean
56
57patternProperties:
58  "^([a-z]*-)?sram@[a-f0-9]+$":
59    type: object
60    description:
61      Each child of the sram node specifies a region of reserved memory.
62    properties:
63      compatible:
64        description:
65          Should contain a vendor specific string in the form
66          <vendor>,[<device>-]<usage>
67        enum:
68          - allwinner,sun9i-a80-smp-sram
69          - amlogic,meson8-smp-sram
70          - amlogic,meson8b-smp-sram
71          - renesas,smp-sram
72          - rockchip,rk3066-smp-sram
73          - samsung,exynos4210-sysram
74          - samsung,exynos4210-sysram-ns
75          - socionext,milbeaut-smp-sram
76
77      reg:
78        description:
79          IO mem address range, relative to the SRAM range.
80        maxItems: 1
81
82      pool:
83        description:
84          Indicates that the particular reserved SRAM area is addressable
85          and in use by another device or devices.
86        type: boolean
87
88      export:
89        description:
90          Indicates that the reserved SRAM area may be accessed outside
91          of the kernel, e.g. by bootloader or userspace.
92        type: boolean
93
94      protect-exec:
95        description: |
96          Same as 'pool' above but with the additional constraint that code
97          will be run from the region and that the memory is maintained as
98          read-only, executable during code execution. NOTE: This region must
99          be page aligned on start and end in order to properly allow
100          manipulation of the page attributes.
101        type: boolean
102
103      label:
104        description:
105          The name for the reserved partition, if omitted, the label is taken
106          from the node name excluding the unit address.
107
108    required:
109      - reg
110
111    additionalProperties: false
112
113required:
114  - compatible
115  - reg
116  - "#address-cells"
117  - "#size-cells"
118  - ranges
119
120additionalProperties: false
121
122examples:
123  - |
124    sram@5c000000 {
125        compatible = "mmio-sram";
126        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
127
128        #address-cells = <1>;
129        #size-cells = <1>;
130        ranges = <0 0x5c000000 0x40000>;
131
132        smp-sram@100 {
133            reg = <0x100 0x50>;
134        };
135
136        device-sram@1000 {
137            reg = <0x1000 0x1000>;
138            pool;
139        };
140
141        exported-sram@20000 {
142            reg = <0x20000 0x20000>;
143            export;
144        };
145    };
146
147  - |
148    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
149    // of the secondary cores. Once the core gets powered up it executes the
150    // code that is residing at some specific location of the SYSRAM.
151    //
152    // Therefore reserved section sub-nodes have to be added to the mmio-sram
153    // declaration. These nodes are of two types depending upon secure or
154    // non-secure execution environment.
155    sram@2020000 {
156        compatible = "mmio-sram";
157        reg = <0x02020000 0x54000>;
158        #address-cells = <1>;
159        #size-cells = <1>;
160        ranges = <0 0x02020000 0x54000>;
161
162        smp-sram@0 {
163            compatible = "samsung,exynos4210-sysram";
164            reg = <0x0 0x1000>;
165        };
166
167        smp-sram@53000 {
168            compatible = "samsung,exynos4210-sysram-ns";
169            reg = <0x53000 0x1000>;
170        };
171    };
172
173  - |
174    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
175    // Once the core gets powered up it executes the code that is residing at a
176    // specific location.
177    //
178    // Therefore a reserved section sub-node has to be added to the mmio-sram
179    // declaration.
180    sram@d9000000 {
181        compatible = "mmio-sram";
182        reg = <0xd9000000 0x20000>;
183        #address-cells = <1>;
184        #size-cells = <1>;
185        ranges = <0 0xd9000000 0x20000>;
186
187        smp-sram@1ff80 {
188            compatible = "amlogic,meson8b-smp-sram";
189            reg = <0x1ff80 0x8>;
190        };
191    };
192
193  - |
194    sram@e63c0000 {
195        compatible = "mmio-sram";
196        reg = <0xe63c0000 0x1000>;
197        #address-cells = <1>;
198        #size-cells = <1>;
199        ranges = <0 0xe63c0000 0x1000>;
200
201        smp-sram@0 {
202            compatible = "renesas,smp-sram";
203            reg = <0 0x10>;
204        };
205    };
206
207  - |
208    sram@10080000 {
209        compatible = "mmio-sram";
210        reg = <0x10080000 0x10000>;
211        #address-cells = <1>;
212        #size-cells = <1>;
213        ranges;
214
215        smp-sram@10080000 {
216            compatible = "rockchip,rk3066-smp-sram";
217            reg = <0x10080000 0x50>;
218        };
219    };
220
221  - |
222    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
223    // primary core (cpu0). Once the core gets powered up it checks if a magic
224    // value is set at a specific location. If it is then the BROM will jump
225    // to the software entry address, instead of executing a standard boot.
226    //
227    // Also there are no "secure-only" properties. The implementation should
228    // check if this SRAM is usable first.
229    sram@20000 {
230        // 256 KiB secure SRAM at 0x20000
231        compatible = "mmio-sram";
232        reg = <0x00020000 0x40000>;
233        #address-cells = <1>;
234        #size-cells = <1>;
235        ranges = <0 0x00020000 0x40000>;
236
237        smp-sram@1000 {
238            // This is checked by BROM to determine if
239            // cpu0 should jump to SMP entry vector
240            compatible = "allwinner,sun9i-a80-smp-sram";
241            reg = <0x1000 0x8>;
242        };
243    };
244
245  - |
246    sram@0 {
247        compatible = "mmio-sram";
248        reg = <0x0 0x10000>;
249        #address-cells = <1>;
250        #size-cells = <1>;
251        ranges = <0 0x0 0x10000>;
252
253        smp-sram@f100 {
254            compatible = "socionext,milbeaut-smp-sram";
255            reg = <0xf100 0x20>;
256        };
257    };
258