1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - atmel,sama5d2-securam
32
33  reg:
34    maxItems: 1
35
36  clocks:
37    description:
38      A list of phandle and clock specifier pair that controls the single
39      SRAM clock.
40
41  "#address-cells":
42    const: 1
43
44  "#size-cells":
45    const: 1
46
47  ranges:
48    description:
49      Should translate from local addresses within the sram to bus addresses.
50
51  no-memory-wc:
52    description:
53      The flag indicating, that SRAM memory region has not to be remapped
54      as write combining. WC is used by default.
55    type: boolean
56
57patternProperties:
58  "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
59    type: object
60    description:
61      Each child of the sram node specifies a region of reserved memory.
62    properties:
63      compatible:
64        description:
65          Should contain a vendor specific string in the form
66          <vendor>,[<device>-]<usage>
67        contains:
68          enum:
69            - allwinner,sun4i-a10-sram-a3-a4
70            - allwinner,sun4i-a10-sram-c1
71            - allwinner,sun4i-a10-sram-d
72            - allwinner,sun9i-a80-smp-sram
73            - allwinner,sun50i-a64-sram-c
74            - amlogic,meson8-smp-sram
75            - amlogic,meson8b-smp-sram
76            - renesas,smp-sram
77            - rockchip,rk3066-smp-sram
78            - samsung,exynos4210-sysram
79            - samsung,exynos4210-sysram-ns
80            - socionext,milbeaut-smp-sram
81
82      reg:
83        description:
84          IO mem address range, relative to the SRAM range.
85        maxItems: 1
86
87      pool:
88        description:
89          Indicates that the particular reserved SRAM area is addressable
90          and in use by another device or devices.
91        type: boolean
92
93      export:
94        description:
95          Indicates that the reserved SRAM area may be accessed outside
96          of the kernel, e.g. by bootloader or userspace.
97        type: boolean
98
99      protect-exec:
100        description: |
101          Same as 'pool' above but with the additional constraint that code
102          will be run from the region and that the memory is maintained as
103          read-only, executable during code execution. NOTE: This region must
104          be page aligned on start and end in order to properly allow
105          manipulation of the page attributes.
106        type: boolean
107
108      label:
109        description:
110          The name for the reserved partition, if omitted, the label is taken
111          from the node name excluding the unit address.
112
113    required:
114      - reg
115
116    additionalProperties: false
117
118required:
119  - compatible
120  - reg
121  - "#address-cells"
122  - "#size-cells"
123  - ranges
124
125additionalProperties: false
126
127examples:
128  - |
129    sram@5c000000 {
130        compatible = "mmio-sram";
131        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
132
133        #address-cells = <1>;
134        #size-cells = <1>;
135        ranges = <0 0x5c000000 0x40000>;
136
137        smp-sram@100 {
138            reg = <0x100 0x50>;
139        };
140
141        device-sram@1000 {
142            reg = <0x1000 0x1000>;
143            pool;
144        };
145
146        exported-sram@20000 {
147            reg = <0x20000 0x20000>;
148            export;
149        };
150    };
151
152  - |
153    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
154    // of the secondary cores. Once the core gets powered up it executes the
155    // code that is residing at some specific location of the SYSRAM.
156    //
157    // Therefore reserved section sub-nodes have to be added to the mmio-sram
158    // declaration. These nodes are of two types depending upon secure or
159    // non-secure execution environment.
160    sram@2020000 {
161        compatible = "mmio-sram";
162        reg = <0x02020000 0x54000>;
163        #address-cells = <1>;
164        #size-cells = <1>;
165        ranges = <0 0x02020000 0x54000>;
166
167        smp-sram@0 {
168            compatible = "samsung,exynos4210-sysram";
169            reg = <0x0 0x1000>;
170        };
171
172        smp-sram@53000 {
173            compatible = "samsung,exynos4210-sysram-ns";
174            reg = <0x53000 0x1000>;
175        };
176    };
177
178  - |
179    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
180    // Once the core gets powered up it executes the code that is residing at a
181    // specific location.
182    //
183    // Therefore a reserved section sub-node has to be added to the mmio-sram
184    // declaration.
185    sram@d9000000 {
186        compatible = "mmio-sram";
187        reg = <0xd9000000 0x20000>;
188        #address-cells = <1>;
189        #size-cells = <1>;
190        ranges = <0 0xd9000000 0x20000>;
191
192        smp-sram@1ff80 {
193            compatible = "amlogic,meson8b-smp-sram";
194            reg = <0x1ff80 0x8>;
195        };
196    };
197
198  - |
199    sram@e63c0000 {
200        compatible = "mmio-sram";
201        reg = <0xe63c0000 0x1000>;
202        #address-cells = <1>;
203        #size-cells = <1>;
204        ranges = <0 0xe63c0000 0x1000>;
205
206        smp-sram@0 {
207            compatible = "renesas,smp-sram";
208            reg = <0 0x10>;
209        };
210    };
211
212  - |
213    sram@10080000 {
214        compatible = "mmio-sram";
215        reg = <0x10080000 0x10000>;
216        #address-cells = <1>;
217        #size-cells = <1>;
218        ranges;
219
220        smp-sram@10080000 {
221            compatible = "rockchip,rk3066-smp-sram";
222            reg = <0x10080000 0x50>;
223        };
224    };
225
226  - |
227    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
228    // primary core (cpu0). Once the core gets powered up it checks if a magic
229    // value is set at a specific location. If it is then the BROM will jump
230    // to the software entry address, instead of executing a standard boot.
231    //
232    // Also there are no "secure-only" properties. The implementation should
233    // check if this SRAM is usable first.
234    sram@20000 {
235        // 256 KiB secure SRAM at 0x20000
236        compatible = "mmio-sram";
237        reg = <0x00020000 0x40000>;
238        #address-cells = <1>;
239        #size-cells = <1>;
240        ranges = <0 0x00020000 0x40000>;
241
242        smp-sram@1000 {
243            // This is checked by BROM to determine if
244            // cpu0 should jump to SMP entry vector
245            compatible = "allwinner,sun9i-a80-smp-sram";
246            reg = <0x1000 0x8>;
247        };
248    };
249
250  - |
251    sram@0 {
252        compatible = "mmio-sram";
253        reg = <0x0 0x10000>;
254        #address-cells = <1>;
255        #size-cells = <1>;
256        ranges = <0 0x0 0x10000>;
257
258        smp-sram@f100 {
259            compatible = "socionext,milbeaut-smp-sram";
260            reg = <0xf100 0x20>;
261        };
262    };
263