1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - atmel,sama5d2-securam
32        - rockchip,rk3288-pmu-sram
33
34  reg:
35    maxItems: 1
36
37  clocks:
38    description:
39      A list of phandle and clock specifier pair that controls the single
40      SRAM clock.
41
42  "#address-cells":
43    const: 1
44
45  "#size-cells":
46    const: 1
47
48  ranges:
49    description:
50      Should translate from local addresses within the sram to bus addresses.
51
52  no-memory-wc:
53    description:
54      The flag indicating, that SRAM memory region has not to be remapped
55      as write combining. WC is used by default.
56    type: boolean
57
58patternProperties:
59  "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
60    type: object
61    description:
62      Each child of the sram node specifies a region of reserved memory.
63    properties:
64      compatible:
65        description:
66          Should contain a vendor specific string in the form
67          <vendor>,[<device>-]<usage>
68        contains:
69          enum:
70            - allwinner,sun4i-a10-sram-a3-a4
71            - allwinner,sun4i-a10-sram-c1
72            - allwinner,sun4i-a10-sram-d
73            - allwinner,sun9i-a80-smp-sram
74            - allwinner,sun50i-a64-sram-c
75            - amlogic,meson8-ao-arc-sram
76            - amlogic,meson8b-ao-arc-sram
77            - amlogic,meson8-smp-sram
78            - amlogic,meson8b-smp-sram
79            - amlogic,meson-gxbb-scp-shmem
80            - amlogic,meson-axg-scp-shmem
81            - renesas,smp-sram
82            - rockchip,rk3066-smp-sram
83            - samsung,exynos4210-sysram
84            - samsung,exynos4210-sysram-ns
85            - socionext,milbeaut-smp-sram
86
87      reg:
88        description:
89          IO mem address range, relative to the SRAM range.
90        maxItems: 1
91
92      pool:
93        description:
94          Indicates that the particular reserved SRAM area is addressable
95          and in use by another device or devices.
96        type: boolean
97
98      export:
99        description:
100          Indicates that the reserved SRAM area may be accessed outside
101          of the kernel, e.g. by bootloader or userspace.
102        type: boolean
103
104      protect-exec:
105        description: |
106          Same as 'pool' above but with the additional constraint that code
107          will be run from the region and that the memory is maintained as
108          read-only, executable during code execution. NOTE: This region must
109          be page aligned on start and end in order to properly allow
110          manipulation of the page attributes.
111        type: boolean
112
113      label:
114        description:
115          The name for the reserved partition, if omitted, the label is taken
116          from the node name excluding the unit address.
117
118    required:
119      - reg
120
121    additionalProperties: false
122
123required:
124  - compatible
125  - reg
126
127if:
128  properties:
129    compatible:
130      contains:
131        const: rockchip,rk3288-pmu-sram
132
133else:
134  required:
135    - "#address-cells"
136    - "#size-cells"
137    - ranges
138
139additionalProperties: false
140
141examples:
142  - |
143    sram@5c000000 {
144        compatible = "mmio-sram";
145        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
146
147        #address-cells = <1>;
148        #size-cells = <1>;
149        ranges = <0 0x5c000000 0x40000>;
150
151        smp-sram@100 {
152            reg = <0x100 0x50>;
153        };
154
155        device-sram@1000 {
156            reg = <0x1000 0x1000>;
157            pool;
158        };
159
160        exported-sram@20000 {
161            reg = <0x20000 0x20000>;
162            export;
163        };
164    };
165
166  - |
167    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
168    // of the secondary cores. Once the core gets powered up it executes the
169    // code that is residing at some specific location of the SYSRAM.
170    //
171    // Therefore reserved section sub-nodes have to be added to the mmio-sram
172    // declaration. These nodes are of two types depending upon secure or
173    // non-secure execution environment.
174    sram@2020000 {
175        compatible = "mmio-sram";
176        reg = <0x02020000 0x54000>;
177        #address-cells = <1>;
178        #size-cells = <1>;
179        ranges = <0 0x02020000 0x54000>;
180
181        smp-sram@0 {
182            compatible = "samsung,exynos4210-sysram";
183            reg = <0x0 0x1000>;
184        };
185
186        smp-sram@53000 {
187            compatible = "samsung,exynos4210-sysram-ns";
188            reg = <0x53000 0x1000>;
189        };
190    };
191
192  - |
193    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
194    // Once the core gets powered up it executes the code that is residing at a
195    // specific location.
196    //
197    // Therefore a reserved section sub-node has to be added to the mmio-sram
198    // declaration.
199    sram@d9000000 {
200        compatible = "mmio-sram";
201        reg = <0xd9000000 0x20000>;
202        #address-cells = <1>;
203        #size-cells = <1>;
204        ranges = <0 0xd9000000 0x20000>;
205
206        smp-sram@1ff80 {
207            compatible = "amlogic,meson8b-smp-sram";
208            reg = <0x1ff80 0x8>;
209        };
210    };
211
212  - |
213    sram@e63c0000 {
214        compatible = "mmio-sram";
215        reg = <0xe63c0000 0x1000>;
216        #address-cells = <1>;
217        #size-cells = <1>;
218        ranges = <0 0xe63c0000 0x1000>;
219
220        smp-sram@0 {
221            compatible = "renesas,smp-sram";
222            reg = <0 0x10>;
223        };
224    };
225
226  - |
227    sram@10080000 {
228        compatible = "mmio-sram";
229        reg = <0x10080000 0x10000>;
230        #address-cells = <1>;
231        #size-cells = <1>;
232        ranges;
233
234        smp-sram@10080000 {
235            compatible = "rockchip,rk3066-smp-sram";
236            reg = <0x10080000 0x50>;
237        };
238    };
239
240  - |
241    // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
242    // resume from maskrom(the 1st level loader). This is a common use of
243    // the "pmu-sram" because it keeps power even in low power states
244    // in the system.
245    sram@ff720000 {
246      compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
247      reg = <0xff720000 0x1000>;
248    };
249
250  - |
251    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
252    // primary core (cpu0). Once the core gets powered up it checks if a magic
253    // value is set at a specific location. If it is then the BROM will jump
254    // to the software entry address, instead of executing a standard boot.
255    //
256    // Also there are no "secure-only" properties. The implementation should
257    // check if this SRAM is usable first.
258    sram@20000 {
259        // 256 KiB secure SRAM at 0x20000
260        compatible = "mmio-sram";
261        reg = <0x00020000 0x40000>;
262        #address-cells = <1>;
263        #size-cells = <1>;
264        ranges = <0 0x00020000 0x40000>;
265
266        smp-sram@1000 {
267            // This is checked by BROM to determine if
268            // cpu0 should jump to SMP entry vector
269            compatible = "allwinner,sun9i-a80-smp-sram";
270            reg = <0x1000 0x8>;
271        };
272    };
273
274  - |
275    sram@0 {
276        compatible = "mmio-sram";
277        reg = <0x0 0x10000>;
278        #address-cells = <1>;
279        #size-cells = <1>;
280        ranges = <0 0x0 0x10000>;
281
282        smp-sram@f100 {
283            compatible = "socionext,milbeaut-smp-sram";
284            reg = <0xf100 0x20>;
285        };
286    };
287