1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - amlogic,meson-gxbb-sram
32        - arm,juno-sram-ns
33        - atmel,sama5d2-securam
34        - rockchip,rk3288-pmu-sram
35
36  reg:
37    maxItems: 1
38
39  clocks:
40    maxItems: 1
41    description:
42      A list of phandle and clock specifier pair that controls the single
43      SRAM clock.
44
45  "#address-cells":
46    const: 1
47
48  "#size-cells":
49    const: 1
50
51  ranges:
52    maxItems: 1
53    description:
54      Should translate from local addresses within the sram to bus addresses.
55
56  no-memory-wc:
57    description:
58      The flag indicating, that SRAM memory region has not to be remapped
59      as write combining. WC is used by default.
60    type: boolean
61
62patternProperties:
63  "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
64    type: object
65    description:
66      Each child of the sram node specifies a region of reserved memory.
67    properties:
68      compatible:
69        description:
70          Should contain a vendor specific string in the form
71          <vendor>,[<device>-]<usage>
72        contains:
73          enum:
74            - allwinner,sun4i-a10-sram-a3-a4
75            - allwinner,sun4i-a10-sram-c1
76            - allwinner,sun4i-a10-sram-d
77            - allwinner,sun9i-a80-smp-sram
78            - allwinner,sun50i-a64-sram-c
79            - amlogic,meson8-ao-arc-sram
80            - amlogic,meson8b-ao-arc-sram
81            - amlogic,meson8-smp-sram
82            - amlogic,meson8b-smp-sram
83            - amlogic,meson-gxbb-scp-shmem
84            - amlogic,meson-axg-scp-shmem
85            - arm,juno-scp-shmem
86            - arm,scmi-shmem
87            - arm,scp-shmem
88            - renesas,smp-sram
89            - rockchip,rk3066-smp-sram
90            - samsung,exynos4210-sysram
91            - samsung,exynos4210-sysram-ns
92            - socionext,milbeaut-smp-sram
93
94      reg:
95        description:
96          IO mem address range, relative to the SRAM range.
97        maxItems: 1
98
99      pool:
100        description:
101          Indicates that the particular reserved SRAM area is addressable
102          and in use by another device or devices.
103        type: boolean
104
105      export:
106        description:
107          Indicates that the reserved SRAM area may be accessed outside
108          of the kernel, e.g. by bootloader or userspace.
109        type: boolean
110
111      protect-exec:
112        description: |
113          Same as 'pool' above but with the additional constraint that code
114          will be run from the region and that the memory is maintained as
115          read-only, executable during code execution. NOTE: This region must
116          be page aligned on start and end in order to properly allow
117          manipulation of the page attributes.
118        type: boolean
119
120      label:
121        description:
122          The name for the reserved partition, if omitted, the label is taken
123          from the node name excluding the unit address.
124
125    required:
126      - reg
127
128    additionalProperties: false
129
130required:
131  - compatible
132  - reg
133
134if:
135  properties:
136    compatible:
137      contains:
138        const: rockchip,rk3288-pmu-sram
139
140else:
141  required:
142    - "#address-cells"
143    - "#size-cells"
144    - ranges
145
146additionalProperties: false
147
148examples:
149  - |
150    sram@5c000000 {
151        compatible = "mmio-sram";
152        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
153
154        #address-cells = <1>;
155        #size-cells = <1>;
156        ranges = <0 0x5c000000 0x40000>;
157
158        smp-sram@100 {
159            reg = <0x100 0x50>;
160        };
161
162        device-sram@1000 {
163            reg = <0x1000 0x1000>;
164            pool;
165        };
166
167        exported-sram@20000 {
168            reg = <0x20000 0x20000>;
169            export;
170        };
171    };
172
173  - |
174    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
175    // of the secondary cores. Once the core gets powered up it executes the
176    // code that is residing at some specific location of the SYSRAM.
177    //
178    // Therefore reserved section sub-nodes have to be added to the mmio-sram
179    // declaration. These nodes are of two types depending upon secure or
180    // non-secure execution environment.
181    sram@2020000 {
182        compatible = "mmio-sram";
183        reg = <0x02020000 0x54000>;
184        #address-cells = <1>;
185        #size-cells = <1>;
186        ranges = <0 0x02020000 0x54000>;
187
188        smp-sram@0 {
189            compatible = "samsung,exynos4210-sysram";
190            reg = <0x0 0x1000>;
191        };
192
193        smp-sram@53000 {
194            compatible = "samsung,exynos4210-sysram-ns";
195            reg = <0x53000 0x1000>;
196        };
197    };
198
199  - |
200    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
201    // Once the core gets powered up it executes the code that is residing at a
202    // specific location.
203    //
204    // Therefore a reserved section sub-node has to be added to the mmio-sram
205    // declaration.
206    sram@d9000000 {
207        compatible = "mmio-sram";
208        reg = <0xd9000000 0x20000>;
209        #address-cells = <1>;
210        #size-cells = <1>;
211        ranges = <0 0xd9000000 0x20000>;
212
213        smp-sram@1ff80 {
214            compatible = "amlogic,meson8b-smp-sram";
215            reg = <0x1ff80 0x8>;
216        };
217    };
218
219  - |
220    sram@e63c0000 {
221        compatible = "mmio-sram";
222        reg = <0xe63c0000 0x1000>;
223        #address-cells = <1>;
224        #size-cells = <1>;
225        ranges = <0 0xe63c0000 0x1000>;
226
227        smp-sram@0 {
228            compatible = "renesas,smp-sram";
229            reg = <0 0x10>;
230        };
231    };
232
233  - |
234    sram@10080000 {
235        compatible = "mmio-sram";
236        reg = <0x10080000 0x10000>;
237        #address-cells = <1>;
238        #size-cells = <1>;
239        ranges;
240
241        smp-sram@10080000 {
242            compatible = "rockchip,rk3066-smp-sram";
243            reg = <0x10080000 0x50>;
244        };
245    };
246
247  - |
248    // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
249    // resume from maskrom(the 1st level loader). This is a common use of
250    // the "pmu-sram" because it keeps power even in low power states
251    // in the system.
252    sram@ff720000 {
253      compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
254      reg = <0xff720000 0x1000>;
255    };
256
257  - |
258    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
259    // primary core (cpu0). Once the core gets powered up it checks if a magic
260    // value is set at a specific location. If it is then the BROM will jump
261    // to the software entry address, instead of executing a standard boot.
262    //
263    // Also there are no "secure-only" properties. The implementation should
264    // check if this SRAM is usable first.
265    sram@20000 {
266        // 256 KiB secure SRAM at 0x20000
267        compatible = "mmio-sram";
268        reg = <0x00020000 0x40000>;
269        #address-cells = <1>;
270        #size-cells = <1>;
271        ranges = <0 0x00020000 0x40000>;
272
273        smp-sram@1000 {
274            // This is checked by BROM to determine if
275            // cpu0 should jump to SMP entry vector
276            compatible = "allwinner,sun9i-a80-smp-sram";
277            reg = <0x1000 0x8>;
278        };
279    };
280
281  - |
282    sram@0 {
283        compatible = "mmio-sram";
284        reg = <0x0 0x10000>;
285        #address-cells = <1>;
286        #size-cells = <1>;
287        ranges = <0 0x0 0x10000>;
288
289        smp-sram@f100 {
290            compatible = "socionext,milbeaut-smp-sram";
291            reg = <0xf100 0x20>;
292        };
293    };
294