1f710b49eSMauro Carvalho Chehab# SPDX-License-Identifier: GPL-2.0 2f710b49eSMauro Carvalho Chehab%YAML 1.2 3f710b49eSMauro Carvalho Chehab--- 4f710b49eSMauro Carvalho Chehab$id: http://devicetree.org/schemas/spmi/spmi.yaml# 5f710b49eSMauro Carvalho Chehab$schema: http://devicetree.org/meta-schemas/core.yaml# 6f710b49eSMauro Carvalho Chehab 7f710b49eSMauro Carvalho Chehabtitle: System Power Management Interface (SPMI) Controller 8f710b49eSMauro Carvalho Chehab 9f710b49eSMauro Carvalho Chehabmaintainers: 10f710b49eSMauro Carvalho Chehab - Stephen Boyd <sboyd@kernel.org> 11f710b49eSMauro Carvalho Chehab 12f710b49eSMauro Carvalho Chehabdescription: | 13f710b49eSMauro Carvalho Chehab The System Power Management (SPMI) controller is a 2-wire bus defined 14f710b49eSMauro Carvalho Chehab by the MIPI Alliance for power management control to be used on SoC designs. 15f710b49eSMauro Carvalho Chehab 16f710b49eSMauro Carvalho Chehab SPMI controllers are modelled in device tree using a generic set of 17f710b49eSMauro Carvalho Chehab bindings defined here, plus any bus controller specific properties, if 18f710b49eSMauro Carvalho Chehab needed. 19f710b49eSMauro Carvalho Chehab 20f710b49eSMauro Carvalho Chehab Each SPMI controller has zero or more child nodes (up to 16 ones), each 21f710b49eSMauro Carvalho Chehab one representing an unique slave at the bus. 22f710b49eSMauro Carvalho Chehab 23f710b49eSMauro Carvalho Chehabproperties: 24f710b49eSMauro Carvalho Chehab $nodename: 25f710b49eSMauro Carvalho Chehab pattern: "^spmi@.*" 26f710b49eSMauro Carvalho Chehab 27f710b49eSMauro Carvalho Chehab reg: 28f710b49eSMauro Carvalho Chehab maxItems: 1 29f710b49eSMauro Carvalho Chehab 30f710b49eSMauro Carvalho Chehab "#address-cells": 31f710b49eSMauro Carvalho Chehab const: 2 32f710b49eSMauro Carvalho Chehab 33f710b49eSMauro Carvalho Chehab "#size-cells": 34f710b49eSMauro Carvalho Chehab const: 0 35f710b49eSMauro Carvalho Chehab 36f710b49eSMauro Carvalho ChehabpatternProperties: 37f710b49eSMauro Carvalho Chehab "@[0-9a-f]$": 38f710b49eSMauro Carvalho Chehab description: up to 16 child PMIC nodes 39f710b49eSMauro Carvalho Chehab type: object 40f710b49eSMauro Carvalho Chehab 41f710b49eSMauro Carvalho Chehab properties: 42f710b49eSMauro Carvalho Chehab reg: 43*dc401475SRob Herring items: 44*dc401475SRob Herring - minItems: 1 45f710b49eSMauro Carvalho Chehab items: 46f710b49eSMauro Carvalho Chehab - minimum: 0 47f710b49eSMauro Carvalho Chehab maximum: 0xf 48f710b49eSMauro Carvalho Chehab - enum: [ 0 ] 49*dc401475SRob Herring description: 50*dc401475SRob Herring 0 means user ID address. 1 is reserved for group ID 51*dc401475SRob Herring address. 52f710b49eSMauro Carvalho Chehab 53f710b49eSMauro Carvalho Chehab required: 54f710b49eSMauro Carvalho Chehab - reg 55f710b49eSMauro Carvalho Chehab 56f710b49eSMauro Carvalho Chehabrequired: 57f710b49eSMauro Carvalho Chehab - reg 58f710b49eSMauro Carvalho Chehab 596a0e321eSRob HerringadditionalProperties: true 606a0e321eSRob Herring 61f710b49eSMauro Carvalho Chehabexamples: 62f710b49eSMauro Carvalho Chehab - | 63f710b49eSMauro Carvalho Chehab #include <dt-bindings/spmi/spmi.h> 64f710b49eSMauro Carvalho Chehab 65f710b49eSMauro Carvalho Chehab spmi@0 { 66f710b49eSMauro Carvalho Chehab reg = <0 0>; 67f710b49eSMauro Carvalho Chehab 68f710b49eSMauro Carvalho Chehab #address-cells = <2>; 69f710b49eSMauro Carvalho Chehab #size-cells = <0>; 70f710b49eSMauro Carvalho Chehab 71f710b49eSMauro Carvalho Chehab child@0 { 72f710b49eSMauro Carvalho Chehab reg = <0 SPMI_USID>; 73f710b49eSMauro Carvalho Chehab }; 74f710b49eSMauro Carvalho Chehab 75f710b49eSMauro Carvalho Chehab child@7 { 76f710b49eSMauro Carvalho Chehab reg = <7 SPMI_USID>; 77f710b49eSMauro Carvalho Chehab }; 78f710b49eSMauro Carvalho Chehab }; 79