1ffa119f7SBenjamin Gaignard# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2ffa119f7SBenjamin Gaignard%YAML 1.2 3ffa119f7SBenjamin Gaignard--- 4ffa119f7SBenjamin Gaignard$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml# 5ffa119f7SBenjamin Gaignard$schema: http://devicetree.org/meta-schemas/core.yaml# 6ffa119f7SBenjamin Gaignard 7ffa119f7SBenjamin Gaignardtitle: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings 8ffa119f7SBenjamin Gaignard 9ffa119f7SBenjamin Gaignardmaintainers: 10*f4eedebdSPatrice Chotard - Christophe Kerello <christophe.kerello@foss.st.com> 11*f4eedebdSPatrice Chotard - Patrice Chotard <patrice.chotard@foss.st.com> 12ffa119f7SBenjamin Gaignard 13ffa119f7SBenjamin GaignardallOf: 14ffa119f7SBenjamin Gaignard - $ref: "spi-controller.yaml#" 15ffa119f7SBenjamin Gaignard 16ffa119f7SBenjamin Gaignardproperties: 17ffa119f7SBenjamin Gaignard compatible: 18ffa119f7SBenjamin Gaignard const: st,stm32f469-qspi 19ffa119f7SBenjamin Gaignard 20ffa119f7SBenjamin Gaignard reg: 21ffa119f7SBenjamin Gaignard items: 22ffa119f7SBenjamin Gaignard - description: registers 23ffa119f7SBenjamin Gaignard - description: memory mapping 24ffa119f7SBenjamin Gaignard 25ffa119f7SBenjamin Gaignard reg-names: 26ffa119f7SBenjamin Gaignard items: 27ffa119f7SBenjamin Gaignard - const: qspi 28ffa119f7SBenjamin Gaignard - const: qspi_mm 29ffa119f7SBenjamin Gaignard 30ffa119f7SBenjamin Gaignard clocks: 31ffa119f7SBenjamin Gaignard maxItems: 1 32ffa119f7SBenjamin Gaignard 33ffa119f7SBenjamin Gaignard interrupts: 34ffa119f7SBenjamin Gaignard maxItems: 1 35ffa119f7SBenjamin Gaignard 36ffa119f7SBenjamin Gaignard resets: 37ffa119f7SBenjamin Gaignard maxItems: 1 38ffa119f7SBenjamin Gaignard 39ffa119f7SBenjamin Gaignard dmas: 40ffa119f7SBenjamin Gaignard items: 41ffa119f7SBenjamin Gaignard - description: tx DMA channel 42ffa119f7SBenjamin Gaignard - description: rx DMA channel 43ffa119f7SBenjamin Gaignard 44ffa119f7SBenjamin Gaignard dma-names: 45ffa119f7SBenjamin Gaignard items: 46ffa119f7SBenjamin Gaignard - const: tx 47ffa119f7SBenjamin Gaignard - const: rx 48ffa119f7SBenjamin Gaignard 49ffa119f7SBenjamin Gaignardrequired: 50ffa119f7SBenjamin Gaignard - compatible 51ffa119f7SBenjamin Gaignard - reg 52ffa119f7SBenjamin Gaignard - reg-names 53ffa119f7SBenjamin Gaignard - clocks 54ffa119f7SBenjamin Gaignard - interrupts 55ffa119f7SBenjamin Gaignard 566fdc6e23SRob HerringunevaluatedProperties: false 576fdc6e23SRob Herring 58ffa119f7SBenjamin Gaignardexamples: 59ffa119f7SBenjamin Gaignard - | 60ffa119f7SBenjamin Gaignard #include <dt-bindings/interrupt-controller/arm-gic.h> 61ffa119f7SBenjamin Gaignard #include <dt-bindings/clock/stm32mp1-clks.h> 62ffa119f7SBenjamin Gaignard #include <dt-bindings/reset/stm32mp1-resets.h> 63ffa119f7SBenjamin Gaignard spi@58003000 { 64ffa119f7SBenjamin Gaignard compatible = "st,stm32f469-qspi"; 65ffa119f7SBenjamin Gaignard reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 66ffa119f7SBenjamin Gaignard reg-names = "qspi", "qspi_mm"; 67ffa119f7SBenjamin Gaignard interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 68ffa119f7SBenjamin Gaignard dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, 69ffa119f7SBenjamin Gaignard <&mdma1 22 0x10 0x100008 0x0 0x0>; 70ffa119f7SBenjamin Gaignard dma-names = "tx", "rx"; 71ffa119f7SBenjamin Gaignard clocks = <&rcc QSPI_K>; 72ffa119f7SBenjamin Gaignard resets = <&rcc QSPI_R>; 73ffa119f7SBenjamin Gaignard 74ffa119f7SBenjamin Gaignard #address-cells = <1>; 75ffa119f7SBenjamin Gaignard #size-cells = <0>; 76ffa119f7SBenjamin Gaignard 77ffa119f7SBenjamin Gaignard flash@0 { 78ffa119f7SBenjamin Gaignard compatible = "jedec,spi-nor"; 79ffa119f7SBenjamin Gaignard reg = <0>; 80ffa119f7SBenjamin Gaignard spi-rx-bus-width = <4>; 81ffa119f7SBenjamin Gaignard spi-max-frequency = <108000000>; 82ffa119f7SBenjamin Gaignard }; 83ffa119f7SBenjamin Gaignard }; 84ffa119f7SBenjamin Gaignard 85ffa119f7SBenjamin Gaignard... 86