1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM PL022 SPI controller
8
9maintainers:
10  - Linus Walleij <linus.walleij@linaro.org>
11
12allOf:
13  - $ref: spi-controller.yaml#
14  - $ref: /schemas/arm/primecell.yaml#
15
16# We need a select here so we don't match all nodes with 'arm,primecell'
17select:
18  properties:
19    compatible:
20      contains:
21        const: arm,pl022
22  required:
23    - compatible
24
25properties:
26  compatible:
27    items:
28      - const: arm,pl022
29      - const: arm,primecell
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  clocks:
38    maxItems: 2
39
40  clock-names:
41    items:
42      - const: sspclk
43      - const: apb_pclk
44
45  pl022,autosuspend-delay:
46    description: delay in ms following transfer completion before the
47      runtime power management system suspends the device. A setting of 0
48      indicates no delay and the device will be suspended immediately.
49    $ref: /schemas/types.yaml#/definitions/uint32
50
51  pl022,rt:
52    description: indicates the controller should run the message pump with realtime
53      priority to minimise the transfer latency on the bus (boolean)
54    type: boolean
55
56  dmas:
57    description:
58      Two or more DMA channel specifiers following the convention outlined
59      in bindings/dma/dma.txt
60    minItems: 2
61    maxItems: 32
62
63  dma-names:
64    description:
65      There must be at least one channel named "tx" for transmit and named "rx"
66      for receive.
67    minItems: 2
68    maxItems: 32
69    additionalItems: true
70    items:
71      - const: rx
72      - const: tx
73
74  resets:
75    maxItems: 1
76
77patternProperties:
78  "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
79    type: object
80    # SPI slave nodes must be children of the SPI master node and can
81    # contain the following properties.
82    properties:
83      pl022,interface:
84        description: SPI interface type
85        $ref: /schemas/types.yaml#/definitions/uint32
86        enum:
87          - 0      # SPI
88          - 1      # Texas Instruments Synchronous Serial Frame Format
89          - 2      # Microwire (Half Duplex)
90
91      pl022,com-mode:
92        description: Specifies the transfer mode
93        $ref: /schemas/types.yaml#/definitions/uint32
94        enum:
95          - 0      # interrupt mode
96          - 1      # polling mode
97          - 2      # DMA mode
98        default: 1
99
100      pl022,rx-level-trig:
101        description: Rx FIFO watermark level
102        $ref: /schemas/types.yaml#/definitions/uint32
103        minimum: 0
104        maximum: 4
105
106      pl022,tx-level-trig:
107        description: Tx FIFO watermark level
108        $ref: /schemas/types.yaml#/definitions/uint32
109        minimum: 0
110        maximum: 4
111
112      pl022,ctrl-len:
113        description: Microwire interface - Control length
114        $ref: /schemas/types.yaml#/definitions/uint32
115        minimum: 0x03
116        maximum: 0x1f
117
118      pl022,wait-state:
119        description: Microwire interface - Wait state
120        $ref: /schemas/types.yaml#/definitions/uint32
121        enum: [0, 1]
122
123      pl022,duplex:
124        description: Microwire interface - Full/Half duplex
125        $ref: /schemas/types.yaml#/definitions/uint32
126        enum: [0, 1]
127
128required:
129  - compatible
130  - reg
131  - interrupts
132
133unevaluatedProperties: false
134
135examples:
136  - |
137    spi@e0100000 {
138      compatible = "arm,pl022", "arm,primecell";
139      reg = <0xe0100000 0x1000>;
140      #address-cells = <1>;
141      #size-cells = <0>;
142      interrupts = <0 31 0x4>;
143      dmas = <&dma_controller 23 1>,
144        <&dma_controller 24 0>;
145      dma-names = "rx", "tx";
146
147      flash@1 {
148        compatible = "st,m25p80";
149        reg = <1>;
150        spi-max-frequency = <12000000>;
151        spi-cpol;
152        spi-cpha;
153        pl022,interface = <0>;
154        pl022,com-mode = <0x2>;
155        pl022,rx-level-trig = <0>;
156        pl022,tx-level-trig = <0>;
157        pl022,ctrl-len = <0x11>;
158        pl022,wait-state = <0>;
159        pl022,duplex = <0>;
160      };
161    };
162...
163