1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Peripheral-specific properties for a SPI bus. 8 9description: 10 Many SPI controllers need to add properties to peripheral devices. They could 11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be 12 controller specific like delay in clock or data lines, etc. These properties 13 need to be defined in the peripheral node because they are per-peripheral and 14 there can be multiple peripherals attached to a controller. All those 15 properties are listed here. The controller specific properties should go in 16 their own separate schema that should be referenced from here. 17 18maintainers: 19 - Pratyush Yadav <p.yadav@ti.com> 20 21properties: 22 reg: 23 minItems: 1 24 maxItems: 256 25 items: 26 items: 27 - minimum: 0 28 maximum: 256 29 description: 30 Chip select used by the device. 31 32 spi-3wire: 33 $ref: /schemas/types.yaml#/definitions/flag 34 description: 35 The device requires 3-wire mode. 36 37 spi-cpha: 38 $ref: /schemas/types.yaml#/definitions/flag 39 description: 40 The device requires shifted clock phase (CPHA) mode. 41 42 spi-cpol: 43 $ref: /schemas/types.yaml#/definitions/flag 44 description: 45 The device requires inverse clock polarity (CPOL) mode. 46 47 spi-cs-high: 48 $ref: /schemas/types.yaml#/definitions/flag 49 description: 50 The device requires the chip select active high. 51 52 spi-lsb-first: 53 $ref: /schemas/types.yaml#/definitions/flag 54 description: 55 The device requires the LSB first mode. 56 57 spi-max-frequency: 58 $ref: /schemas/types.yaml#/definitions/uint32 59 description: 60 Maximum SPI clocking speed of the device in Hz. 61 62 spi-rx-bus-width: 63 description: 64 Bus width to the SPI bus used for read transfers. 65 If 0 is provided, then no RX will be possible on this device. 66 $ref: /schemas/types.yaml#/definitions/uint32 67 enum: [0, 1, 2, 4, 8] 68 default: 1 69 70 spi-rx-delay-us: 71 description: 72 Delay, in microseconds, after a read transfer. 73 74 spi-tx-bus-width: 75 description: 76 Bus width to the SPI bus used for write transfers. 77 If 0 is provided, then no TX will be possible on this device. 78 $ref: /schemas/types.yaml#/definitions/uint32 79 enum: [0, 1, 2, 4, 8] 80 default: 1 81 82 spi-tx-delay-us: 83 description: 84 Delay, in microseconds, after a write transfer. 85 86 stacked-memories: 87 description: Several SPI memories can be wired in stacked mode. 88 This basically means that either a device features several chip 89 selects, or that different devices must be seen as a single 90 bigger chip. This basically doubles (or more) the total address 91 space with only a single additional wire, while still needing 92 to repeat the commands when crossing a chip boundary. The size of 93 each chip should be provided as members of the array. 94 $ref: /schemas/types.yaml#/definitions/uint64-array 95 minItems: 2 96 maxItems: 4 97 98 parallel-memories: 99 description: Several SPI memories can be wired in parallel mode. 100 The devices are physically on a different buses but will always 101 act synchronously as each data word is spread across the 102 different memories (eg. even bits are stored in one memory, odd 103 bits in the other). This basically doubles the address space and 104 the throughput while greatly complexifying the wiring because as 105 many busses as devices must be wired. The size of each chip should 106 be provided as members of the array. 107 $ref: /schemas/types.yaml#/definitions/uint64-array 108 minItems: 2 109 maxItems: 4 110 111# The controller specific properties go here. 112allOf: 113 - $ref: cdns,qspi-nor-peripheral-props.yaml# 114 - $ref: samsung,spi-peripheral-props.yaml# 115 116additionalProperties: true 117