16b52c00fSDavid DaneyCavium, Inc. OCTEON SOC SPI master controller. 26b52c00fSDavid Daney 36b52c00fSDavid DaneyRequired properties: 46b52c00fSDavid Daney- compatible : "cavium,octeon-3010-spi" 56b52c00fSDavid Daney- reg : The register base for the controller. 66b52c00fSDavid Daney- interrupts : One interrupt, used by the controller. 76b52c00fSDavid Daney- #address-cells : <1>, as required by generic SPI binding. 86b52c00fSDavid Daney- #size-cells : <0>, also as required by generic SPI binding. 96b52c00fSDavid Daney 106b52c00fSDavid DaneyChild nodes as per the generic SPI binding. 116b52c00fSDavid Daney 126b52c00fSDavid DaneyExample: 136b52c00fSDavid Daney 146b52c00fSDavid Daney spi@1070000001000 { 156b52c00fSDavid Daney compatible = "cavium,octeon-3010-spi"; 166b52c00fSDavid Daney reg = <0x10700 0x00001000 0x0 0x100>; 176b52c00fSDavid Daney interrupts = <0 58>; 186b52c00fSDavid Daney #address-cells = <1>; 196b52c00fSDavid Daney #size-cells = <0>; 206b52c00fSDavid Daney 216b52c00fSDavid Daney eeprom@0 { 226b52c00fSDavid Daney compatible = "st,m95256", "atmel,at25"; 236b52c00fSDavid Daney reg = <0>; 246b52c00fSDavid Daney spi-max-frequency = <5000000>; 256b52c00fSDavid Daney spi-cpha; 266b52c00fSDavid Daney spi-cpol; 276b52c00fSDavid Daney 286b52c00fSDavid Daney pagesize = <64>; 296b52c00fSDavid Daney size = <32768>; 306b52c00fSDavid Daney address-width = <16>; 316b52c00fSDavid Daney }; 326b52c00fSDavid Daney }; 336b52c00fSDavid Daney 34