1ARM Freescale DSPI controller
2
3Required properties:
4- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
5		"fsl,ls2085a-dspi"
6		or
7		"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
8		"fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
9		"fsl,ls1088a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
10- reg : Offset and length of the register set for the device
11- interrupts : Should contain SPI controller interrupt
12- clocks: from common clock binding: handle to dspi clock.
13- clock-names: from common clock binding: Shall be "dspi".
14- pinctrl-0: pin control group to be used for this controller.
15- pinctrl-names: must contain a "default" entry.
16- spi-num-chipselects : the number of the chipselect signals.
17- bus-num : the slave chip chipselect signal number.
18
19Optional property:
20- big-endian: If present the dspi device's registers are implemented
21  in big endian mode.
22
23Optional SPI slave node properties:
24- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
25  select and the start of clock signal, at the start of a transfer.
26- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
27  signal and deactivating chip select, at the end of a transfer.
28
29Example:
30
31dspi0@4002c000 {
32	#address-cells = <1>;
33	#size-cells = <0>;
34	compatible = "fsl,vf610-dspi";
35	reg = <0x4002c000 0x1000>;
36	interrupts = <0 67 0x04>;
37	clocks = <&clks VF610_CLK_DSPI0>;
38	clock-names = "dspi";
39	spi-num-chipselects = <5>;
40	bus-num = <0>;
41	pinctrl-names = "default";
42	pinctrl-0 = <&pinctrl_dspi0_1>;
43	big-endian;
44
45	sflash: at26df081a@0 {
46		#address-cells = <1>;
47		#size-cells = <1>;
48		compatible = "atmel,at26df081a";
49		spi-max-frequency = <16000000>;
50		spi-cpol;
51		spi-cpha;
52		reg = <0>;
53		linux,modalias = "m25p80";
54		modal = "at26df081a";
55		fsl,spi-cs-sck-delay = <100>;
56		fsl,spi-sck-cs-delay = <50>;
57	};
58};
59
60
61