1Davinci SPI controller device bindings
2
3Required properties:
4- #address-cells: number of cells required to define a chip select
5	address on the SPI bus. Should be set to 1.
6- #size-cells: should be zero.
7- compatible:
8	- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
9	- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
10- reg: Offset and length of SPI controller register space
11- num-cs: Number of chip selects. This includes internal as well as
12	GPIO chip selects.
13- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
14	IP to the interrupt controller within the SoC. Possible values
15	are 0 and 1. Manual says one of the two possible interrupt
16	lines can be tied to the interrupt controller. Set this
17	based on a specifc SoC configuration.
18- interrupts: interrupt number mapped to CPU.
19- clocks: spi clk phandle
20
21Optional:
22- cs-gpios: gpio chip selects
23	For example to have 3 internal CS and 2 GPIO CS, user could define
24	cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
25	where first three are internal CS and last two are GPIO CS.
26
27Example of a NOR flash slave device (n25q032) connected to DaVinci
28SPI controller device over the SPI bus.
29
30spi0:spi@20BF0000 {
31	#address-cells			= <1>;
32	#size-cells			= <0>;
33	compatible			= "ti,dm6446-spi";
34	reg				= <0x20BF0000 0x1000>;
35	num-cs				= <4>;
36	ti,davinci-spi-intr-line	= <0>;
37	interrupts			= <338>;
38	clocks				= <&clkspi>;
39
40	flash: n25q032@0 {
41		#address-cells = <1>;
42		#size-cells = <1>;
43		compatible = "st,m25p32";
44		spi-max-frequency = <25000000>;
45		reg = <0>;
46
47		partition@0 {
48			label = "u-boot-spl";
49			reg = <0x0 0x80000>;
50			read-only;
51		};
52
53		partition@1 {
54			label = "test";
55			reg = <0x80000 0x380000>;
56		};
57	};
58};
59