1eed48556SMurali KaricheriDavinci SPI controller device bindings 2eed48556SMurali Karicheri 3eed48556SMurali KaricheriRequired properties: 4eed48556SMurali Karicheri- #address-cells: number of cells required to define a chip select 5eed48556SMurali Karicheri address on the SPI bus. Should be set to 1. 6eed48556SMurali Karicheri- #size-cells: should be zero. 7eed48556SMurali Karicheri- compatible: 8eed48556SMurali Karicheri - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family 9eed48556SMurali Karicheri - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family 10eed48556SMurali Karicheri- reg: Offset and length of SPI controller register space 11a88e34eaSMurali Karicheri- num-cs: Number of chip selects. This includes internal as well as 12a88e34eaSMurali Karicheri GPIO chip selects. 13eed48556SMurali Karicheri- ti,davinci-spi-intr-line: interrupt line used to connect the SPI 14eed48556SMurali Karicheri IP to the interrupt controller within the SoC. Possible values 15eed48556SMurali Karicheri are 0 and 1. Manual says one of the two possible interrupt 16eed48556SMurali Karicheri lines can be tied to the interrupt controller. Set this 17eed48556SMurali Karicheri based on a specifc SoC configuration. 18eed48556SMurali Karicheri- interrupts: interrupt number mapped to CPU. 19eed48556SMurali Karicheri- clocks: spi clk phandle 20eed48556SMurali Karicheri 21a88e34eaSMurali KaricheriOptional: 22a88e34eaSMurali Karicheri- cs-gpios: gpio chip selects 23a88e34eaSMurali Karicheri For example to have 3 internal CS and 2 GPIO CS, user could define 24a88e34eaSMurali Karicheri cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; 25a88e34eaSMurali Karicheri where first three are internal CS and last two are GPIO CS. 26a88e34eaSMurali Karicheri 27eed48556SMurali KaricheriExample of a NOR flash slave device (n25q032) connected to DaVinci 28eed48556SMurali KaricheriSPI controller device over the SPI bus. 29eed48556SMurali Karicheri 30eed48556SMurali Karicherispi0:spi@20BF0000 { 31eed48556SMurali Karicheri #address-cells = <1>; 32eed48556SMurali Karicheri #size-cells = <0>; 33eed48556SMurali Karicheri compatible = "ti,dm6446-spi"; 34eed48556SMurali Karicheri reg = <0x20BF0000 0x1000>; 35eed48556SMurali Karicheri num-cs = <4>; 36eed48556SMurali Karicheri ti,davinci-spi-intr-line = <0>; 37eed48556SMurali Karicheri interrupts = <338>; 38eed48556SMurali Karicheri clocks = <&clkspi>; 39eed48556SMurali Karicheri 40eed48556SMurali Karicheri flash: n25q032@0 { 41eed48556SMurali Karicheri #address-cells = <1>; 42eed48556SMurali Karicheri #size-cells = <1>; 43eed48556SMurali Karicheri compatible = "st,m25p32"; 44eed48556SMurali Karicheri spi-max-frequency = <25000000>; 45eed48556SMurali Karicheri reg = <0>; 46eed48556SMurali Karicheri 47eed48556SMurali Karicheri partition@0 { 48eed48556SMurali Karicheri label = "u-boot-spl"; 49eed48556SMurali Karicheri reg = <0x0 0x80000>; 50eed48556SMurali Karicheri read-only; 51eed48556SMurali Karicheri }; 52eed48556SMurali Karicheri 53eed48556SMurali Karicheri partition@1 { 54eed48556SMurali Karicheri label = "test"; 55eed48556SMurali Karicheri reg = <0x80000 0x380000>; 56eed48556SMurali Karicheri }; 57eed48556SMurali Karicheri }; 58eed48556SMurali Karicheri}; 59