1eed48556SMurali KaricheriDavinci SPI controller device bindings 2eed48556SMurali Karicheri 3365a7bb3SMurali KaricheriLinks on DM: 4365a7bb3SMurali KaricheriKeystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf 5365a7bb3SMurali Karicheridm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf 6365a7bb3SMurali KaricheriOMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf 7365a7bb3SMurali Karicheri 8eed48556SMurali KaricheriRequired properties: 9eed48556SMurali Karicheri- #address-cells: number of cells required to define a chip select 10eed48556SMurali Karicheri address on the SPI bus. Should be set to 1. 11eed48556SMurali Karicheri- #size-cells: should be zero. 12eed48556SMurali Karicheri- compatible: 13eed48556SMurali Karicheri - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family 14eed48556SMurali Karicheri - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family 15eed48556SMurali Karicheri- reg: Offset and length of SPI controller register space 16a88e34eaSMurali Karicheri- num-cs: Number of chip selects. This includes internal as well as 17a88e34eaSMurali Karicheri GPIO chip selects. 18eed48556SMurali Karicheri- ti,davinci-spi-intr-line: interrupt line used to connect the SPI 19eed48556SMurali Karicheri IP to the interrupt controller within the SoC. Possible values 20eed48556SMurali Karicheri are 0 and 1. Manual says one of the two possible interrupt 21eed48556SMurali Karicheri lines can be tied to the interrupt controller. Set this 22eed48556SMurali Karicheri based on a specifc SoC configuration. 23eed48556SMurali Karicheri- interrupts: interrupt number mapped to CPU. 24eed48556SMurali Karicheri- clocks: spi clk phandle 25eed48556SMurali Karicheri 26a88e34eaSMurali KaricheriOptional: 27a88e34eaSMurali Karicheri- cs-gpios: gpio chip selects 28a88e34eaSMurali Karicheri For example to have 3 internal CS and 2 GPIO CS, user could define 29a88e34eaSMurali Karicheri cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; 30a88e34eaSMurali Karicheri where first three are internal CS and last two are GPIO CS. 31a88e34eaSMurali Karicheri 32365a7bb3SMurali KaricheriOptional properties for slave devices: 33365a7bb3SMurali KaricheriSPI slave nodes can contain the following properties. 34365a7bb3SMurali KaricheriNot all SPI Peripherals from Texas Instruments support this. 35365a7bb3SMurali KaricheriPlease check SPI peripheral documentation for a device before using these. 36365a7bb3SMurali Karicheri 37365a7bb3SMurali Karicheri- ti,spi-wdelay : delay between transmission of words 38365a7bb3SMurali Karicheri (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module 39365a7bb3SMurali Karicheri clock periods. 40365a7bb3SMurali Karicheri 41365a7bb3SMurali Karicheri delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period 42365a7bb3SMurali Karicheri 43365a7bb3SMurali KaricheriBelow is timing diagram which shows functional meaning of 44365a7bb3SMurali Karicheri"ti,spi-wdelay" parameter. 45365a7bb3SMurali Karicheri 46365a7bb3SMurali Karicheri +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ 47365a7bb3SMurali KaricheriSPI_CLK | | | | | | | | | | | | | | | | 48365a7bb3SMurali Karicheri +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +- 49365a7bb3SMurali Karicheri 50365a7bb3SMurali KaricheriSPI_SOMI/SIMO+-----------------+ +----------- 51365a7bb3SMurali Karicheri +----------+ word1 +---------------------------+word2 52365a7bb3SMurali Karicheri +-----------------+ +----------- 53365a7bb3SMurali Karicheri WDELAY 54365a7bb3SMurali Karicheri <--------------------------> 55365a7bb3SMurali Karicheri 56eed48556SMurali KaricheriExample of a NOR flash slave device (n25q032) connected to DaVinci 57eed48556SMurali KaricheriSPI controller device over the SPI bus. 58eed48556SMurali Karicheri 59eed48556SMurali Karicherispi0:spi@20BF0000 { 60eed48556SMurali Karicheri #address-cells = <1>; 61eed48556SMurali Karicheri #size-cells = <0>; 62eed48556SMurali Karicheri compatible = "ti,dm6446-spi"; 63eed48556SMurali Karicheri reg = <0x20BF0000 0x1000>; 64eed48556SMurali Karicheri num-cs = <4>; 65eed48556SMurali Karicheri ti,davinci-spi-intr-line = <0>; 66eed48556SMurali Karicheri interrupts = <338>; 67eed48556SMurali Karicheri clocks = <&clkspi>; 68eed48556SMurali Karicheri 69eed48556SMurali Karicheri flash: n25q032@0 { 70eed48556SMurali Karicheri #address-cells = <1>; 71eed48556SMurali Karicheri #size-cells = <1>; 72eed48556SMurali Karicheri compatible = "st,m25p32"; 73eed48556SMurali Karicheri spi-max-frequency = <25000000>; 74eed48556SMurali Karicheri reg = <0>; 75365a7bb3SMurali Karicheri ti,spi-wdelay = <8>; 76eed48556SMurali Karicheri 77eed48556SMurali Karicheri partition@0 { 78eed48556SMurali Karicheri label = "u-boot-spl"; 79eed48556SMurali Karicheri reg = <0x0 0x80000>; 80eed48556SMurali Karicheri read-only; 81eed48556SMurali Karicheri }; 82eed48556SMurali Karicheri 83eed48556SMurali Karicheri partition@1 { 84eed48556SMurali Karicheri label = "test"; 85eed48556SMurali Karicheri reg = <0x80000 0x380000>; 86eed48556SMurali Karicheri }; 87eed48556SMurali Karicheri }; 88eed48556SMurali Karicheri}; 89