1eed48556SMurali KaricheriDavinci SPI controller device bindings 2eed48556SMurali Karicheri 3365a7bb3SMurali KaricheriLinks on DM: 4365a7bb3SMurali KaricheriKeystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf 5365a7bb3SMurali Karicheridm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf 6365a7bb3SMurali KaricheriOMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf 7365a7bb3SMurali Karicheri 8eed48556SMurali KaricheriRequired properties: 9eed48556SMurali Karicheri- #address-cells: number of cells required to define a chip select 10eed48556SMurali Karicheri address on the SPI bus. Should be set to 1. 11eed48556SMurali Karicheri- #size-cells: should be zero. 12eed48556SMurali Karicheri- compatible: 13eed48556SMurali Karicheri - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family 14eed48556SMurali Karicheri - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family 15fa466c91SFranklin S Cooper Jr - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC 16fa466c91SFranklin S Cooper Jr family 17eed48556SMurali Karicheri- reg: Offset and length of SPI controller register space 18a88e34eaSMurali Karicheri- num-cs: Number of chip selects. This includes internal as well as 19a88e34eaSMurali Karicheri GPIO chip selects. 20eed48556SMurali Karicheri- ti,davinci-spi-intr-line: interrupt line used to connect the SPI 21eed48556SMurali Karicheri IP to the interrupt controller within the SoC. Possible values 22eed48556SMurali Karicheri are 0 and 1. Manual says one of the two possible interrupt 23eed48556SMurali Karicheri lines can be tied to the interrupt controller. Set this 240fb7620fSMasanari Iida based on a specific SoC configuration. 25eed48556SMurali Karicheri- interrupts: interrupt number mapped to CPU. 26eed48556SMurali Karicheri- clocks: spi clk phandle 2732c30f73SFranklin Cooper For 66AK2G this property should be set per binding, 2832c30f73SFranklin Cooper Documentation/devicetree/bindings/clock/ti,sci-clk.txt 2932c30f73SFranklin Cooper 3032c30f73SFranklin CooperSoC-specific Required Properties: 3132c30f73SFranklin Cooper 3232c30f73SFranklin CooperThe following are mandatory properties for Keystone 2 66AK2G SoCs only: 3332c30f73SFranklin Cooper 3432c30f73SFranklin Cooper- power-domains: Should contain a phandle to a PM domain provider node 3532c30f73SFranklin Cooper and an args specifier containing the SPI device id 3632c30f73SFranklin Cooper value. This property is as per the binding, 37eed48556SMurali Karicheri 38a88e34eaSMurali KaricheriOptional: 39a88e34eaSMurali Karicheri- cs-gpios: gpio chip selects 40a88e34eaSMurali Karicheri For example to have 3 internal CS and 2 GPIO CS, user could define 41a88e34eaSMurali Karicheri cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; 42a88e34eaSMurali Karicheri where first three are internal CS and last two are GPIO CS. 43a88e34eaSMurali Karicheri 44365a7bb3SMurali KaricheriOptional properties for slave devices: 45365a7bb3SMurali KaricheriSPI slave nodes can contain the following properties. 46365a7bb3SMurali KaricheriNot all SPI Peripherals from Texas Instruments support this. 47365a7bb3SMurali KaricheriPlease check SPI peripheral documentation for a device before using these. 48365a7bb3SMurali Karicheri 49365a7bb3SMurali Karicheri- ti,spi-wdelay : delay between transmission of words 50365a7bb3SMurali Karicheri (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module 51365a7bb3SMurali Karicheri clock periods. 52365a7bb3SMurali Karicheri 53365a7bb3SMurali Karicheri delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period 54365a7bb3SMurali Karicheri 55365a7bb3SMurali KaricheriBelow is timing diagram which shows functional meaning of 56365a7bb3SMurali Karicheri"ti,spi-wdelay" parameter. 57365a7bb3SMurali Karicheri 58365a7bb3SMurali Karicheri +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ 59365a7bb3SMurali KaricheriSPI_CLK | | | | | | | | | | | | | | | | 60365a7bb3SMurali Karicheri +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +- 61365a7bb3SMurali Karicheri 62365a7bb3SMurali KaricheriSPI_SOMI/SIMO+-----------------+ +----------- 63365a7bb3SMurali Karicheri +----------+ word1 +---------------------------+word2 64365a7bb3SMurali Karicheri +-----------------+ +----------- 65365a7bb3SMurali Karicheri WDELAY 66365a7bb3SMurali Karicheri <--------------------------> 67365a7bb3SMurali Karicheri 68eed48556SMurali KaricheriExample of a NOR flash slave device (n25q032) connected to DaVinci 69eed48556SMurali KaricheriSPI controller device over the SPI bus. 70eed48556SMurali Karicheri 71eed48556SMurali Karicherispi0:spi@20BF0000 { 72eed48556SMurali Karicheri #address-cells = <1>; 73eed48556SMurali Karicheri #size-cells = <0>; 74eed48556SMurali Karicheri compatible = "ti,dm6446-spi"; 75eed48556SMurali Karicheri reg = <0x20BF0000 0x1000>; 76eed48556SMurali Karicheri num-cs = <4>; 77eed48556SMurali Karicheri ti,davinci-spi-intr-line = <0>; 78eed48556SMurali Karicheri interrupts = <338>; 79eed48556SMurali Karicheri clocks = <&clkspi>; 80eed48556SMurali Karicheri 81eed48556SMurali Karicheri flash: n25q032@0 { 82eed48556SMurali Karicheri #address-cells = <1>; 83eed48556SMurali Karicheri #size-cells = <1>; 84eed48556SMurali Karicheri compatible = "st,m25p32"; 85eed48556SMurali Karicheri spi-max-frequency = <25000000>; 86eed48556SMurali Karicheri reg = <0>; 87365a7bb3SMurali Karicheri ti,spi-wdelay = <8>; 88eed48556SMurali Karicheri 89eed48556SMurali Karicheri partition@0 { 90eed48556SMurali Karicheri label = "u-boot-spl"; 91eed48556SMurali Karicheri reg = <0x0 0x80000>; 92eed48556SMurali Karicheri read-only; 93eed48556SMurali Karicheri }; 94eed48556SMurali Karicheri 95eed48556SMurali Karicheri partition@1 { 96eed48556SMurali Karicheri label = "test"; 97eed48556SMurali Karicheri reg = <0x80000 0x380000>; 98eed48556SMurali Karicheri }; 99eed48556SMurali Karicheri }; 100eed48556SMurali Karicheri}; 101