1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/spi-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: SPI Controller Generic Binding 8 9maintainers: 10 - Mark Brown <broonie@kernel.org> 11 12description: | 13 SPI busses can be described with a node for the SPI controller device 14 and a set of child nodes for each SPI slave on the bus. The system SPI 15 controller may be described for use in SPI master mode or in SPI slave mode, 16 but not for both at the same time. 17 18properties: 19 $nodename: 20 pattern: "^spi(@.*|-[0-9a-f])*$" 21 22 "#address-cells": 23 const: 1 24 25 "#size-cells": 26 const: 0 27 28 cs-gpios: 29 description: | 30 GPIOs used as chip selects. 31 If that property is used, the number of chip selects will be 32 increased automatically with max(cs-gpios, hardware chip selects). 33 34 So if, for example, the controller has 2 CS lines, and the 35 cs-gpios looks like this 36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; 37 38 Then it should be configured so that num_chipselect = 4, with 39 the following mapping 40 cs0 : &gpio1 0 0 41 cs1 : native 42 cs2 : &gpio1 1 0 43 cs3 : &gpio1 2 0 44 45 num-cs: 46 $ref: /schemas/types.yaml#/definitions/uint32 47 description: 48 Total number of chip selects. 49 50 spi-slave: 51 $ref: /schemas/types.yaml#/definitions/flag 52 description: 53 The SPI controller acts as a slave, instead of a master. 54 55patternProperties: 56 "^slave$": 57 type: object 58 59 properties: 60 compatible: 61 description: 62 Compatible of the SPI device. 63 64 required: 65 - compatible 66 67 "^.*@[0-9a-f]+$": 68 type: object 69 70 properties: 71 compatible: 72 description: 73 Compatible of the SPI device. 74 75 reg: 76 maxItems: 1 77 minimum: 0 78 maximum: 256 79 description: 80 Chip select used by the device. 81 82 spi-3wire: 83 $ref: /schemas/types.yaml#/definitions/flag 84 description: 85 The device requires 3-wire mode. 86 87 spi-cpha: 88 $ref: /schemas/types.yaml#/definitions/flag 89 description: 90 The device requires shifted clock phase (CPHA) mode. 91 92 spi-cpol: 93 $ref: /schemas/types.yaml#/definitions/flag 94 description: 95 The device requires inverse clock polarity (CPOL) mode. 96 97 spi-cs-high: 98 $ref: /schemas/types.yaml#/definitions/flag 99 description: 100 The device requires the chip select active high. 101 102 spi-lsb-first: 103 $ref: /schemas/types.yaml#/definitions/flag 104 description: 105 The device requires the LSB first mode. 106 107 spi-max-frequency: 108 $ref: /schemas/types.yaml#/definitions/uint32 109 description: 110 Maximum SPI clocking speed of the device in Hz. 111 112 spi-rx-bus-width: 113 allOf: 114 - $ref: /schemas/types.yaml#/definitions/uint32 115 - enum: [ 1, 2, 4 ] 116 - default: 1 117 description: 118 Bus width to the SPI bus used for MISO. 119 120 spi-rx-delay-us: 121 description: 122 Delay, in microseconds, after a read transfer. 123 124 spi-tx-bus-width: 125 allOf: 126 - $ref: /schemas/types.yaml#/definitions/uint32 127 - enum: [ 1, 2, 4 ] 128 - default: 1 129 description: 130 Bus width to the SPI bus used for MOSI. 131 132 spi-tx-delay-us: 133 description: 134 Delay, in microseconds, after a write transfer. 135 136 required: 137 - compatible 138 - reg 139 140examples: 141 - | 142 spi@f00 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 146 reg = <0xf00 0x20>; 147 interrupts = <2 13 0 2 14 0>; 148 interrupt-parent = <&mpc5200_pic>; 149 150 ethernet-switch@0 { 151 compatible = "micrel,ks8995m"; 152 spi-max-frequency = <1000000>; 153 reg = <0>; 154 }; 155 156 codec@1 { 157 compatible = "ti,tlv320aic26"; 158 spi-max-frequency = <100000>; 159 reg = <1>; 160 }; 161 }; 162