1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface 8 9maintainers: 10 - Mark Brown <broonie@kernel.org> 11 12allOf: 13 - $ref: spi-controller.yaml# 14 - if: 15 properties: 16 compatible: 17 contains: 18 enum: 19 - mscc,ocelot-spi 20 - mscc,jaguar2-spi 21 then: 22 properties: 23 reg: 24 minItems: 2 25 - if: 26 properties: 27 compatible: 28 contains: 29 enum: 30 - baikal,bt1-sys-ssi 31 then: 32 properties: 33 mux-controls: 34 maxItems: 1 35 required: 36 - mux-controls 37 else: 38 required: 39 - interrupts 40 41properties: 42 compatible: 43 oneOf: 44 - description: Generic DW SPI Controller 45 enum: 46 - snps,dw-apb-ssi 47 - snps,dwc-ssi-1.01a 48 - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller 49 items: 50 - enum: 51 - mscc,ocelot-spi 52 - mscc,jaguar2-spi 53 - const: snps,dw-apb-ssi 54 - description: Microchip Sparx5 SoC SPI Controller 55 const: microchip,sparx5-spi 56 - description: Amazon Alpine SPI Controller 57 const: amazon,alpine-dw-apb-ssi 58 - description: Renesas RZ/N1 SPI Controller 59 items: 60 - const: renesas,rzn1-spi 61 - const: snps,dw-apb-ssi 62 - description: Intel Keem Bay SPI Controller 63 const: intel,keembay-ssi 64 - description: Intel Thunder Bay SPI Controller 65 const: intel,thunderbay-ssi 66 - description: Baikal-T1 SPI Controller 67 const: baikal,bt1-ssi 68 - description: Baikal-T1 System Boot SPI Controller 69 const: baikal,bt1-sys-ssi 70 - description: Canaan Kendryte K210 SoS SPI Controller 71 const: canaan,k210-spi 72 - description: Renesas RZ/N1 SPI Controller 73 items: 74 - enum: 75 - renesas,r9a06g032-spi # RZ/N1D 76 - renesas,r9a06g033-spi # RZ/N1S 77 - const: renesas,rzn1-spi # RZ/N1 78 79 reg: 80 minItems: 1 81 items: 82 - description: DW APB SSI controller memory mapped registers 83 - description: SPI MST region map or directly mapped SPI ROM 84 85 interrupts: 86 maxItems: 1 87 88 clocks: 89 minItems: 1 90 items: 91 - description: SPI Controller reference clock source 92 - description: APB interface clock source 93 94 clock-names: 95 minItems: 1 96 items: 97 - const: ssi_clk 98 - const: pclk 99 100 resets: 101 maxItems: 1 102 103 reset-names: 104 const: spi 105 106 reg-io-width: 107 description: I/O register width (in bytes) implemented by this device 108 default: 4 109 enum: [ 2, 4 ] 110 111 num-cs: 112 default: 4 113 minimum: 1 114 maximum: 4 115 116 dmas: 117 items: 118 - description: TX DMA Channel 119 - description: RX DMA Channel 120 121 dma-names: 122 items: 123 - const: tx 124 - const: rx 125 126 rx-sample-delay-ns: 127 default: 0 128 description: | 129 Default value of the rx-sample-delay-ns property. 130 This value will be used if the property is not explicitly defined 131 for a SPI slave device. 132 133 SPI Rx sample delay offset, unit is nanoseconds. 134 The delay from the default sample time before the actual sample of the 135 rxd input signal occurs. The "rx_sample_delay" is an optional feature 136 of the designware controller, and the upper limit is also subject to 137 controller configuration. 138 139patternProperties: 140 "^.*@[0-9a-f]+$": 141 type: object 142 properties: 143 reg: 144 minimum: 0 145 maximum: 3 146 147unevaluatedProperties: false 148 149required: 150 - compatible 151 - reg 152 - "#address-cells" 153 - "#size-cells" 154 - clocks 155 156examples: 157 - | 158 spi@fff00000 { 159 compatible = "snps,dw-apb-ssi"; 160 reg = <0xfff00000 0x1000>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 interrupts = <0 154 4>; 164 clocks = <&spi_m_clk>; 165 num-cs = <2>; 166 cs-gpios = <&gpio0 13 0>, 167 <&gpio0 14 0>; 168 rx-sample-delay-ns = <3>; 169 flash@1 { 170 compatible = "spi-nand"; 171 reg = <1>; 172 rx-sample-delay-ns = <7>; 173 }; 174 }; 175 - | 176 spi@1f040100 { 177 compatible = "baikal,bt1-sys-ssi"; 178 reg = <0x1f040100 0x900>, 179 <0x1c000000 0x1000000>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 mux-controls = <&boot_mux>; 183 clocks = <&ccu_sys>; 184 clock-names = "ssi_clk"; 185 }; 186... 187