1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas MSIOF SPI controller 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12allOf: 13 - $ref: spi-controller.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5 20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible 21 # device 22 - items: 23 - enum: 24 - renesas,msiof-r8a7743 # RZ/G1M 25 - renesas,msiof-r8a7744 # RZ/G1N 26 - renesas,msiof-r8a7745 # RZ/G1E 27 - renesas,msiof-r8a77470 # RZ/G1C 28 - renesas,msiof-r8a7790 # R-Car H2 29 - renesas,msiof-r8a7791 # R-Car M2-W 30 - renesas,msiof-r8a7792 # R-Car V2H 31 - renesas,msiof-r8a7793 # R-Car M2-N 32 - renesas,msiof-r8a7794 # R-Car E2 33 - const: renesas,rcar-gen2-msiof # generic R-Car Gen2 and RZ/G1 34 # compatible device 35 - items: 36 - enum: 37 - renesas,msiof-r8a774a1 # RZ/G2M 38 - renesas,msiof-r8a774b1 # RZ/G2N 39 - renesas,msiof-r8a774c0 # RZ/G2E 40 - renesas,msiof-r8a7795 # R-Car H3 41 - renesas,msiof-r8a7796 # R-Car M3-W 42 - renesas,msiof-r8a77965 # R-Car M3-N 43 - renesas,msiof-r8a77970 # R-Car V3M 44 - renesas,msiof-r8a77980 # R-Car V3H 45 - renesas,msiof-r8a77990 # R-Car E3 46 - renesas,msiof-r8a77995 # R-Car D3 47 - const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2 48 # compatible device 49 - items: 50 - const: renesas,sh-msiof # deprecated 51 52 reg: 53 minItems: 1 54 maxItems: 2 55 oneOf: 56 - items: 57 - description: CPU and DMA engine registers 58 - items: 59 - description: CPU registers 60 - description: DMA engine registers 61 62 interrupts: 63 maxItems: 1 64 65 clocks: 66 maxItems: 1 67 68 num-cs: 69 description: | 70 Total number of chip selects (default is 1). 71 Up to 3 native chip selects are supported: 72 0: MSIOF_SYNC 73 1: MSIOF_SS1 74 2: MSIOF_SS2 75 Hardware limitations related to chip selects: 76 - Native chip selects are always deasserted in between transfers 77 that are part of the same message. Use cs-gpios to work around 78 this. 79 - All slaves using native chip selects must use the same spi-cs-high 80 configuration. Use cs-gpios to work around this. 81 - When using GPIO chip selects, at least one native chip select must 82 be left unused, as it will be driven anyway. 83 minimum: 1 84 maximum: 3 85 default: 1 86 87 dmas: 88 minItems: 2 89 maxItems: 4 90 91 dma-names: 92 minItems: 2 93 maxItems: 4 94 items: 95 enum: [ tx, rx ] 96 97 renesas,dtdl: 98 description: delay sync signal (setup) in transmit mode. 99 allOf: 100 - $ref: /schemas/types.yaml#/definitions/uint32 101 - enum: 102 - 0 # no bit delay 103 - 50 # 0.5-clock-cycle delay 104 - 100 # 1-clock-cycle delay 105 - 150 # 1.5-clock-cycle delay 106 - 200 # 2-clock-cycle delay 107 108 renesas,syncdl: 109 description: delay sync signal (hold) in transmit mode 110 allOf: 111 - $ref: /schemas/types.yaml#/definitions/uint32 112 - enum: 113 - 0 # no bit delay 114 - 50 # 0.5-clock-cycle delay 115 - 100 # 1-clock-cycle delay 116 - 150 # 1.5-clock-cycle delay 117 - 200 # 2-clock-cycle delay 118 - 300 # 3-clock-cycle delay 119 120 renesas,tx-fifo-size: 121 # deprecated for soctype-specific bindings 122 description: | 123 Override the default TX fifo size. Unit is words. Ignored if 0. 124 allOf: 125 - $ref: /schemas/types.yaml#/definitions/uint32 126 - maxItems: 1 127 default: 64 128 129 renesas,rx-fifo-size: 130 # deprecated for soctype-specific bindings 131 description: | 132 Override the default RX fifo size. Unit is words. Ignored if 0. 133 allOf: 134 - $ref: /schemas/types.yaml#/definitions/uint32 135 - maxItems: 1 136 default: 64 137 138required: 139 - compatible 140 - reg 141 - interrupts 142 - '#address-cells' 143 - '#size-cells' 144 145examples: 146 - | 147 #include <dt-bindings/clock/r8a7791-clock.h> 148 #include <dt-bindings/interrupt-controller/irq.h> 149 150 msiof0: spi@e6e20000 { 151 compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof"; 152 reg = <0 0xe6e20000 0 0x0064>; 153 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 155 dmas = <&dmac0 0x51>, <&dmac0 0x52>; 156 dma-names = "tx", "rx"; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 }; 160