1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas MSIOF SPI controller 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12allOf: 13 - $ref: spi-controller.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5 20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible 21 # device 22 - items: 23 - enum: 24 - renesas,msiof-r8a7742 # RZ/G1H 25 - renesas,msiof-r8a7743 # RZ/G1M 26 - renesas,msiof-r8a7744 # RZ/G1N 27 - renesas,msiof-r8a7745 # RZ/G1E 28 - renesas,msiof-r8a77470 # RZ/G1C 29 - renesas,msiof-r8a7790 # R-Car H2 30 - renesas,msiof-r8a7791 # R-Car M2-W 31 - renesas,msiof-r8a7792 # R-Car V2H 32 - renesas,msiof-r8a7793 # R-Car M2-N 33 - renesas,msiof-r8a7794 # R-Car E2 34 - const: renesas,rcar-gen2-msiof # generic R-Car Gen2 and RZ/G1 35 # compatible device 36 - items: 37 - enum: 38 - renesas,msiof-r8a774a1 # RZ/G2M 39 - renesas,msiof-r8a774b1 # RZ/G2N 40 - renesas,msiof-r8a774c0 # RZ/G2E 41 - renesas,msiof-r8a774e1 # RZ/G2H 42 - renesas,msiof-r8a7795 # R-Car H3 43 - renesas,msiof-r8a7796 # R-Car M3-W 44 - renesas,msiof-r8a77961 # R-Car M3-W+ 45 - renesas,msiof-r8a77965 # R-Car M3-N 46 - renesas,msiof-r8a77970 # R-Car V3M 47 - renesas,msiof-r8a77980 # R-Car V3H 48 - renesas,msiof-r8a77990 # R-Car E3 49 - renesas,msiof-r8a77995 # R-Car D3 50 - const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2 51 # compatible device 52 - items: 53 - enum: 54 - renesas,msiof-r8a779a0 # R-Car V3U 55 - renesas,msiof-r8a779f0 # R-Car S4-8 56 - const: renesas,rcar-gen4-msiof # generic R-Car Gen4 57 # compatible device 58 - items: 59 - const: renesas,sh-msiof # deprecated 60 61 reg: 62 minItems: 1 63 maxItems: 2 64 oneOf: 65 - items: 66 - description: CPU and DMA engine registers 67 - items: 68 - description: CPU registers 69 - description: DMA engine registers 70 71 interrupts: 72 maxItems: 1 73 74 clocks: 75 maxItems: 1 76 77 power-domains: 78 maxItems: 1 79 80 resets: 81 maxItems: 1 82 83 num-cs: 84 description: | 85 Total number of chip selects (default is 1). 86 Up to 3 native chip selects are supported: 87 0: MSIOF_SYNC 88 1: MSIOF_SS1 89 2: MSIOF_SS2 90 Hardware limitations related to chip selects: 91 - Native chip selects are always deasserted in between transfers 92 that are part of the same message. Use cs-gpios to work around 93 this. 94 - All slaves using native chip selects must use the same spi-cs-high 95 configuration. Use cs-gpios to work around this. 96 - When using GPIO chip selects, at least one native chip select must 97 be left unused, as it will be driven anyway. 98 minimum: 1 99 maximum: 3 100 default: 1 101 102 dmas: 103 minItems: 2 104 maxItems: 4 105 106 dma-names: 107 minItems: 2 108 maxItems: 4 109 items: 110 enum: [ tx, rx ] 111 112 renesas,dtdl: 113 description: delay sync signal (setup) in transmit mode. 114 $ref: /schemas/types.yaml#/definitions/uint32 115 enum: 116 - 0 # no bit delay 117 - 50 # 0.5-clock-cycle delay 118 - 100 # 1-clock-cycle delay 119 - 150 # 1.5-clock-cycle delay 120 - 200 # 2-clock-cycle delay 121 122 renesas,syncdl: 123 description: delay sync signal (hold) in transmit mode 124 $ref: /schemas/types.yaml#/definitions/uint32 125 enum: 126 - 0 # no bit delay 127 - 50 # 0.5-clock-cycle delay 128 - 100 # 1-clock-cycle delay 129 - 150 # 1.5-clock-cycle delay 130 - 200 # 2-clock-cycle delay 131 - 300 # 3-clock-cycle delay 132 133 renesas,tx-fifo-size: 134 # deprecated for soctype-specific bindings 135 description: | 136 Override the default TX fifo size. Unit is words. Ignored if 0. 137 $ref: /schemas/types.yaml#/definitions/uint32 138 default: 64 139 140 renesas,rx-fifo-size: 141 # deprecated for soctype-specific bindings 142 description: | 143 Override the default RX fifo size. Unit is words. Ignored if 0. 144 $ref: /schemas/types.yaml#/definitions/uint32 145 default: 64 146 147required: 148 - compatible 149 - reg 150 - interrupts 151 - '#address-cells' 152 - '#size-cells' 153 154unevaluatedProperties: false 155 156examples: 157 - | 158 #include <dt-bindings/clock/r8a7791-clock.h> 159 #include <dt-bindings/interrupt-controller/irq.h> 160 161 msiof0: spi@e6e20000 { 162 compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof"; 163 reg = <0xe6e20000 0x0064>; 164 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 166 dmas = <&dmac0 0x51>, <&dmac0 0x52>; 167 dma-names = "tx", "rx"; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 }; 171