1*14dde074SFabrizio Castro# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*14dde074SFabrizio Castro%YAML 1.2 3*14dde074SFabrizio Castro--- 4*14dde074SFabrizio Castro$id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml# 5*14dde074SFabrizio Castro$schema: http://devicetree.org/meta-schemas/core.yaml# 6*14dde074SFabrizio Castro 7*14dde074SFabrizio Castrotitle: Renesas RZ/V2M Clocked Serial Interface (CSI) 8*14dde074SFabrizio Castro 9*14dde074SFabrizio Castromaintainers: 10*14dde074SFabrizio Castro - Fabrizio Castro <fabrizio.castro.jz@renesas.com> 11*14dde074SFabrizio Castro - Geert Uytterhoeven <geert+renesas@glider.be> 12*14dde074SFabrizio Castro 13*14dde074SFabrizio CastroallOf: 14*14dde074SFabrizio Castro - $ref: spi-controller.yaml# 15*14dde074SFabrizio Castro 16*14dde074SFabrizio Castroproperties: 17*14dde074SFabrizio Castro compatible: 18*14dde074SFabrizio Castro const: renesas,rzv2m-csi 19*14dde074SFabrizio Castro 20*14dde074SFabrizio Castro reg: 21*14dde074SFabrizio Castro maxItems: 1 22*14dde074SFabrizio Castro 23*14dde074SFabrizio Castro interrupts: 24*14dde074SFabrizio Castro maxItems: 1 25*14dde074SFabrizio Castro 26*14dde074SFabrizio Castro clocks: 27*14dde074SFabrizio Castro items: 28*14dde074SFabrizio Castro - description: The clock used to generate the output clock (CSICLK) 29*14dde074SFabrizio Castro - description: Internal clock to access the registers (PCLK) 30*14dde074SFabrizio Castro 31*14dde074SFabrizio Castro clock-names: 32*14dde074SFabrizio Castro items: 33*14dde074SFabrizio Castro - const: csiclk 34*14dde074SFabrizio Castro - const: pclk 35*14dde074SFabrizio Castro 36*14dde074SFabrizio Castro resets: 37*14dde074SFabrizio Castro maxItems: 1 38*14dde074SFabrizio Castro 39*14dde074SFabrizio Castro power-domains: 40*14dde074SFabrizio Castro maxItems: 1 41*14dde074SFabrizio Castro 42*14dde074SFabrizio Castrorequired: 43*14dde074SFabrizio Castro - compatible 44*14dde074SFabrizio Castro - reg 45*14dde074SFabrizio Castro - interrupts 46*14dde074SFabrizio Castro - clocks 47*14dde074SFabrizio Castro - clock-names 48*14dde074SFabrizio Castro - resets 49*14dde074SFabrizio Castro - power-domains 50*14dde074SFabrizio Castro - '#address-cells' 51*14dde074SFabrizio Castro - '#size-cells' 52*14dde074SFabrizio Castro 53*14dde074SFabrizio CastrounevaluatedProperties: false 54*14dde074SFabrizio Castro 55*14dde074SFabrizio Castroexamples: 56*14dde074SFabrizio Castro - | 57*14dde074SFabrizio Castro #include <dt-bindings/interrupt-controller/arm-gic.h> 58*14dde074SFabrizio Castro #include <dt-bindings/clock/r9a09g011-cpg.h> 59*14dde074SFabrizio Castro csi4: spi@a4020200 { 60*14dde074SFabrizio Castro compatible = "renesas,rzv2m-csi"; 61*14dde074SFabrizio Castro reg = <0xa4020200 0x80>; 62*14dde074SFabrizio Castro interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 63*14dde074SFabrizio Castro clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>, 64*14dde074SFabrizio Castro <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; 65*14dde074SFabrizio Castro clock-names = "csiclk", "pclk"; 66*14dde074SFabrizio Castro resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; 67*14dde074SFabrizio Castro power-domains = <&cpg>; 68*14dde074SFabrizio Castro #address-cells = <1>; 69*14dde074SFabrizio Castro #size-cells = <0>; 70*14dde074SFabrizio Castro }; 71