1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Qualcomm Quad Serial Peripheral Interface (QSPI) 9 10maintainers: 11 - Mukesh Savaliya <msavaliy@codeaurora.org> 12 - Akash Asthana <akashast@codeaurora.org> 13 14description: 15 The QSPI controller allows SPI protocol communication in single, dual, or quad 16 wire transmission modes for read/write access to slaves such as NOR flash. 17 18allOf: 19 - $ref: /spi/spi-controller.yaml# 20 21properties: 22 compatible: 23 items: 24 - const: qcom,sdm845-qspi 25 - const: qcom,qspi-v1 26 27 reg: 28 maxItems: 1 29 30 interrupts: 31 maxItems: 1 32 33 clock-names: 34 items: 35 - const: iface 36 - const: core 37 38 clocks: 39 items: 40 - description: AHB clock 41 - description: QSPI core clock 42 43required: 44 - compatible 45 - reg 46 - interrupts 47 - clock-names 48 - clocks 49 50examples: 51 - | 52 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 53 #include <dt-bindings/interrupt-controller/arm-gic.h> 54 55 soc: soc@0 { 56 #address-cells = <2>; 57 #size-cells = <2>; 58 59 qspi: spi@88df000 { 60 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 61 reg = <0 0x88df000 0 0x600>; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 65 clock-names = "iface", "core"; 66 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 67 <&gcc GCC_QSPI_CORE_CLK>; 68 69 flash@0 { 70 compatible = "jedec,spi-nor"; 71 reg = <0>; 72 spi-max-frequency = <25000000>; 73 spi-tx-bus-width = <2>; 74 spi-rx-bus-width = <2>; 75 }; 76 77 }; 78 }; 79... 80