1d2423aa0SAkash Asthana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2d2423aa0SAkash Asthana 3d2423aa0SAkash Asthana%YAML 1.2 4d2423aa0SAkash Asthana--- 5d2423aa0SAkash Asthana$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" 6d2423aa0SAkash Asthana$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7d2423aa0SAkash Asthana 8d2423aa0SAkash Asthanatitle: Qualcomm Quad Serial Peripheral Interface (QSPI) 9d2423aa0SAkash Asthana 10d2423aa0SAkash Asthanamaintainers: 11d2423aa0SAkash Asthana - Mukesh Savaliya <msavaliy@codeaurora.org> 12d2423aa0SAkash Asthana - Akash Asthana <akashast@codeaurora.org> 13d2423aa0SAkash Asthana 14d2423aa0SAkash Asthanadescription: 15d2423aa0SAkash Asthana The QSPI controller allows SPI protocol communication in single, dual, or quad 16d2423aa0SAkash Asthana wire transmission modes for read/write access to slaves such as NOR flash. 17d2423aa0SAkash Asthana 18d2423aa0SAkash AsthanaallOf: 19d2423aa0SAkash Asthana - $ref: /spi/spi-controller.yaml# 20d2423aa0SAkash Asthana 21d2423aa0SAkash Asthanaproperties: 22d2423aa0SAkash Asthana compatible: 23d2423aa0SAkash Asthana items: 24d2423aa0SAkash Asthana - const: qcom,sdm845-qspi 25d2423aa0SAkash Asthana - const: qcom,qspi-v1 26d2423aa0SAkash Asthana 27d2423aa0SAkash Asthana reg: 28d2423aa0SAkash Asthana maxItems: 1 29d2423aa0SAkash Asthana 30d2423aa0SAkash Asthana interrupts: 31d2423aa0SAkash Asthana maxItems: 1 32d2423aa0SAkash Asthana 33d2423aa0SAkash Asthana clock-names: 34d2423aa0SAkash Asthana items: 35d2423aa0SAkash Asthana - const: iface 36d2423aa0SAkash Asthana - const: core 37d2423aa0SAkash Asthana 38d2423aa0SAkash Asthana clocks: 39d2423aa0SAkash Asthana items: 40d2423aa0SAkash Asthana - description: AHB clock 41d2423aa0SAkash Asthana - description: QSPI core clock 42d2423aa0SAkash Asthana 438f9c2915SAkash Asthana interconnects: 448f9c2915SAkash Asthana minItems: 1 458f9c2915SAkash Asthana maxItems: 2 468f9c2915SAkash Asthana 478f9c2915SAkash Asthana interconnect-names: 488f9c2915SAkash Asthana items: 498f9c2915SAkash Asthana - const: qspi-config 508f9c2915SAkash Asthana - const: qspi-memory 518f9c2915SAkash Asthana 52d2423aa0SAkash Asthanarequired: 53d2423aa0SAkash Asthana - compatible 54d2423aa0SAkash Asthana - reg 55d2423aa0SAkash Asthana - interrupts 56d2423aa0SAkash Asthana - clock-names 57d2423aa0SAkash Asthana - clocks 58d2423aa0SAkash Asthana 59d2423aa0SAkash Asthanaexamples: 60d2423aa0SAkash Asthana - | 61d2423aa0SAkash Asthana #include <dt-bindings/clock/qcom,gcc-sdm845.h> 62d2423aa0SAkash Asthana #include <dt-bindings/interrupt-controller/arm-gic.h> 63d2423aa0SAkash Asthana 64f88d59fcSRob Herring soc: soc { 65d2423aa0SAkash Asthana #address-cells = <2>; 66d2423aa0SAkash Asthana #size-cells = <2>; 67d2423aa0SAkash Asthana 68d2423aa0SAkash Asthana qspi: spi@88df000 { 69d2423aa0SAkash Asthana compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 70d2423aa0SAkash Asthana reg = <0 0x88df000 0 0x600>; 71d2423aa0SAkash Asthana #address-cells = <1>; 72d2423aa0SAkash Asthana #size-cells = <0>; 73d2423aa0SAkash Asthana interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 74d2423aa0SAkash Asthana clock-names = "iface", "core"; 75d2423aa0SAkash Asthana clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 76d2423aa0SAkash Asthana <&gcc GCC_QSPI_CORE_CLK>; 77d2423aa0SAkash Asthana 78d2423aa0SAkash Asthana flash@0 { 79d2423aa0SAkash Asthana compatible = "jedec,spi-nor"; 80d2423aa0SAkash Asthana reg = <0>; 81d2423aa0SAkash Asthana spi-max-frequency = <25000000>; 82d2423aa0SAkash Asthana spi-tx-bus-width = <2>; 83d2423aa0SAkash Asthana spi-rx-bus-width = <2>; 84d2423aa0SAkash Asthana }; 85d2423aa0SAkash Asthana 86d2423aa0SAkash Asthana }; 87d2423aa0SAkash Asthana }; 88d2423aa0SAkash Asthana... 89