1d2423aa0SAkash Asthana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2d2423aa0SAkash Asthana 3d2423aa0SAkash Asthana%YAML 1.2 4d2423aa0SAkash Asthana--- 5d2423aa0SAkash Asthana$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" 6d2423aa0SAkash Asthana$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7d2423aa0SAkash Asthana 8d2423aa0SAkash Asthanatitle: Qualcomm Quad Serial Peripheral Interface (QSPI) 9d2423aa0SAkash Asthana 10d2423aa0SAkash Asthanamaintainers: 11*92298ea3SKrzysztof Kozlowski - Bjorn Andersson <bjorn.andersson@linaro.org> 12d2423aa0SAkash Asthana 139f60a65bSRob Herringdescription: The QSPI controller allows SPI protocol communication in single, 149f60a65bSRob Herring dual, or quad wire transmission modes for read/write access to slaves such 159f60a65bSRob Herring as NOR flash. 16d2423aa0SAkash Asthana 17d2423aa0SAkash AsthanaallOf: 1822a41e9aSRob Herring - $ref: /schemas/spi/spi-controller.yaml# 19d2423aa0SAkash Asthana 20d2423aa0SAkash Asthanaproperties: 21d2423aa0SAkash Asthana compatible: 22d2423aa0SAkash Asthana items: 23eca17cbaSRajesh Patil - enum: 24acde4081SRajesh Patil - qcom,sc7180-qspi 25eca17cbaSRajesh Patil - qcom,sc7280-qspi 26eca17cbaSRajesh Patil - qcom,sdm845-qspi 27eca17cbaSRajesh Patil 28d2423aa0SAkash Asthana - const: qcom,qspi-v1 29d2423aa0SAkash Asthana 30d2423aa0SAkash Asthana reg: 31d2423aa0SAkash Asthana maxItems: 1 32d2423aa0SAkash Asthana 33d2423aa0SAkash Asthana interrupts: 34d2423aa0SAkash Asthana maxItems: 1 35d2423aa0SAkash Asthana 36d2423aa0SAkash Asthana clock-names: 37d2423aa0SAkash Asthana items: 38d2423aa0SAkash Asthana - const: iface 39d2423aa0SAkash Asthana - const: core 40d2423aa0SAkash Asthana 41d2423aa0SAkash Asthana clocks: 42d2423aa0SAkash Asthana items: 43d2423aa0SAkash Asthana - description: AHB clock 44d2423aa0SAkash Asthana - description: QSPI core clock 45d2423aa0SAkash Asthana 468f9c2915SAkash Asthana interconnects: 478f9c2915SAkash Asthana minItems: 1 488f9c2915SAkash Asthana maxItems: 2 498f9c2915SAkash Asthana 508f9c2915SAkash Asthana interconnect-names: 518f9c2915SAkash Asthana items: 528f9c2915SAkash Asthana - const: qspi-config 538f9c2915SAkash Asthana - const: qspi-memory 548f9c2915SAkash Asthana 55d2423aa0SAkash Asthanarequired: 56d2423aa0SAkash Asthana - compatible 57d2423aa0SAkash Asthana - reg 58d2423aa0SAkash Asthana - interrupts 59d2423aa0SAkash Asthana - clock-names 60d2423aa0SAkash Asthana - clocks 61d2423aa0SAkash Asthana 626fdc6e23SRob HerringunevaluatedProperties: false 636fdc6e23SRob Herring 64d2423aa0SAkash Asthanaexamples: 65d2423aa0SAkash Asthana - | 66d2423aa0SAkash Asthana #include <dt-bindings/clock/qcom,gcc-sdm845.h> 67d2423aa0SAkash Asthana #include <dt-bindings/interrupt-controller/arm-gic.h> 68d2423aa0SAkash Asthana 69f88d59fcSRob Herring soc: soc { 70d2423aa0SAkash Asthana #address-cells = <2>; 71d2423aa0SAkash Asthana #size-cells = <2>; 72d2423aa0SAkash Asthana 73d2423aa0SAkash Asthana qspi: spi@88df000 { 74d2423aa0SAkash Asthana compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 75d2423aa0SAkash Asthana reg = <0 0x88df000 0 0x600>; 76d2423aa0SAkash Asthana #address-cells = <1>; 77d2423aa0SAkash Asthana #size-cells = <0>; 78d2423aa0SAkash Asthana interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 79d2423aa0SAkash Asthana clock-names = "iface", "core"; 80d2423aa0SAkash Asthana clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 81d2423aa0SAkash Asthana <&gcc GCC_QSPI_CORE_CLK>; 82d2423aa0SAkash Asthana 83d2423aa0SAkash Asthana flash@0 { 84d2423aa0SAkash Asthana compatible = "jedec,spi-nor"; 85d2423aa0SAkash Asthana reg = <0>; 86d2423aa0SAkash Asthana spi-max-frequency = <25000000>; 87d2423aa0SAkash Asthana spi-tx-bus-width = <2>; 88d2423aa0SAkash Asthana spi-rx-bus-width = <2>; 89d2423aa0SAkash Asthana }; 90d2423aa0SAkash Asthana 91d2423aa0SAkash Asthana }; 92d2423aa0SAkash Asthana }; 93d2423aa0SAkash Asthana... 94