1d2423aa0SAkash Asthana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2d2423aa0SAkash Asthana
3d2423aa0SAkash Asthana%YAML 1.2
4d2423aa0SAkash Asthana---
5d2423aa0SAkash Asthana$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
6d2423aa0SAkash Asthana$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7d2423aa0SAkash Asthana
8d2423aa0SAkash Asthanatitle: Qualcomm Quad Serial Peripheral Interface (QSPI)
9d2423aa0SAkash Asthana
10d2423aa0SAkash Asthanamaintainers:
11d2423aa0SAkash Asthana  - Mukesh Savaliya <msavaliy@codeaurora.org>
12d2423aa0SAkash Asthana  - Akash Asthana <akashast@codeaurora.org>
13d2423aa0SAkash Asthana
149f60a65bSRob Herringdescription: The QSPI controller allows SPI protocol communication in single,
159f60a65bSRob Herring  dual, or quad wire transmission modes for read/write access to slaves such
169f60a65bSRob Herring  as NOR flash.
17d2423aa0SAkash Asthana
18d2423aa0SAkash AsthanaallOf:
19*22a41e9aSRob Herring  - $ref: /schemas/spi/spi-controller.yaml#
20d2423aa0SAkash Asthana
21d2423aa0SAkash Asthanaproperties:
22d2423aa0SAkash Asthana  compatible:
23d2423aa0SAkash Asthana    items:
24eca17cbaSRajesh Patil      - enum:
25acde4081SRajesh Patil          - qcom,sc7180-qspi
26eca17cbaSRajesh Patil          - qcom,sc7280-qspi
27eca17cbaSRajesh Patil          - qcom,sdm845-qspi
28eca17cbaSRajesh Patil
29d2423aa0SAkash Asthana      - const: qcom,qspi-v1
30d2423aa0SAkash Asthana
31d2423aa0SAkash Asthana  reg:
32d2423aa0SAkash Asthana    maxItems: 1
33d2423aa0SAkash Asthana
34d2423aa0SAkash Asthana  interrupts:
35d2423aa0SAkash Asthana    maxItems: 1
36d2423aa0SAkash Asthana
37d2423aa0SAkash Asthana  clock-names:
38d2423aa0SAkash Asthana    items:
39d2423aa0SAkash Asthana      - const: iface
40d2423aa0SAkash Asthana      - const: core
41d2423aa0SAkash Asthana
42d2423aa0SAkash Asthana  clocks:
43d2423aa0SAkash Asthana    items:
44d2423aa0SAkash Asthana      - description: AHB clock
45d2423aa0SAkash Asthana      - description: QSPI core clock
46d2423aa0SAkash Asthana
478f9c2915SAkash Asthana  interconnects:
488f9c2915SAkash Asthana    minItems: 1
498f9c2915SAkash Asthana    maxItems: 2
508f9c2915SAkash Asthana
518f9c2915SAkash Asthana  interconnect-names:
528f9c2915SAkash Asthana    items:
538f9c2915SAkash Asthana      - const: qspi-config
548f9c2915SAkash Asthana      - const: qspi-memory
558f9c2915SAkash Asthana
56d2423aa0SAkash Asthanarequired:
57d2423aa0SAkash Asthana  - compatible
58d2423aa0SAkash Asthana  - reg
59d2423aa0SAkash Asthana  - interrupts
60d2423aa0SAkash Asthana  - clock-names
61d2423aa0SAkash Asthana  - clocks
62d2423aa0SAkash Asthana
636fdc6e23SRob HerringunevaluatedProperties: false
646fdc6e23SRob Herring
65d2423aa0SAkash Asthanaexamples:
66d2423aa0SAkash Asthana  - |
67d2423aa0SAkash Asthana    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
68d2423aa0SAkash Asthana    #include <dt-bindings/interrupt-controller/arm-gic.h>
69d2423aa0SAkash Asthana
70f88d59fcSRob Herring    soc: soc {
71d2423aa0SAkash Asthana        #address-cells = <2>;
72d2423aa0SAkash Asthana        #size-cells = <2>;
73d2423aa0SAkash Asthana
74d2423aa0SAkash Asthana        qspi: spi@88df000 {
75d2423aa0SAkash Asthana            compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
76d2423aa0SAkash Asthana            reg = <0 0x88df000 0 0x600>;
77d2423aa0SAkash Asthana            #address-cells = <1>;
78d2423aa0SAkash Asthana            #size-cells = <0>;
79d2423aa0SAkash Asthana            interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
80d2423aa0SAkash Asthana            clock-names = "iface", "core";
81d2423aa0SAkash Asthana            clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
82d2423aa0SAkash Asthana                         <&gcc GCC_QSPI_CORE_CLK>;
83d2423aa0SAkash Asthana
84d2423aa0SAkash Asthana            flash@0 {
85d2423aa0SAkash Asthana                compatible = "jedec,spi-nor";
86d2423aa0SAkash Asthana                reg = <0>;
87d2423aa0SAkash Asthana                spi-max-frequency = <25000000>;
88d2423aa0SAkash Asthana                spi-tx-bus-width = <2>;
89d2423aa0SAkash Asthana                spi-rx-bus-width = <2>;
90d2423aa0SAkash Asthana            };
91d2423aa0SAkash Asthana
92d2423aa0SAkash Asthana        };
93d2423aa0SAkash Asthana    };
94d2423aa0SAkash Asthana...
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