1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
8
9maintainers:
10  - Andy Gross <agross@kernel.org>
11  - Bjorn Andersson <bjorn.andersson@linaro.org>
12  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13
14description:
15  The QUP v3 core is a GENI based AHB slave that provides a common data path
16  (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
17  mini-core.
18
19  SPI in master mode supports up to 50MHz, up to four chip selects,
20  programmable data path from 4 bits to 32 bits and numerous protocol variants.
21
22  SPI Controller nodes must be child of GENI based Qualcomm Universal
23  Peripharal. Please refer GENI based QUP wrapper controller node bindings
24  described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
25
26allOf:
27  - $ref: /schemas/spi/spi-controller.yaml#
28
29properties:
30  compatible:
31    const: qcom,geni-spi
32
33  clocks:
34    maxItems: 1
35
36  clock-names:
37    const: se
38
39  dmas:
40    maxItems: 2
41
42  dma-names:
43    items:
44      - const: tx
45      - const: rx
46
47  interconnects:
48    maxItems: 2
49
50  interconnect-names:
51    items:
52      - const: qup-core
53      - const: qup-config
54
55  interrupts:
56    maxItems: 1
57
58  operating-points-v2: true
59
60  power-domains:
61    maxItems: 1
62
63  reg:
64    maxItems: 1
65
66required:
67  - compatible
68  - clocks
69  - clock-names
70  - interrupts
71  - reg
72
73unevaluatedProperties: false
74
75examples:
76  - |
77    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
78    #include <dt-bindings/interconnect/qcom,sc7180.h>
79    #include <dt-bindings/interrupt-controller/arm-gic.h>
80    #include <dt-bindings/power/qcom-rpmpd.h>
81
82    spi@880000 {
83        compatible = "qcom,geni-spi";
84        reg = <0x00880000 0x4000>;
85        clock-names = "se";
86        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
87        pinctrl-names = "default";
88        pinctrl-0 = <&qup_spi0_default>;
89        interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
90        #address-cells = <1>;
91        #size-cells = <0>;
92        power-domains = <&rpmhpd SC7180_CX>;
93        operating-points-v2 = <&qup_opp_table>;
94        interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
95                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
96        interconnect-names = "qup-core", "qup-config";
97    };
98
99  - |
100    #include <dt-bindings/dma/qcom-gpi.h>
101
102    spi@884000 {
103        compatible = "qcom,geni-spi";
104        reg = <0x00884000 0x4000>;
105        clock-names = "se";
106        clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
107        dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
108               <&gpi_dma0 1 1 QCOM_GPI_SPI>;
109        dma-names = "tx", "rx";
110        pinctrl-names = "default";
111        pinctrl-0 = <&qup_spi1_default>;
112        interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
113        #address-cells = <1>;
114        #size-cells = <0>;
115    };
116