1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra20/30 SLINK controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  compatible:
15    enum:
16      - nvidia,tegra20-slink
17      - nvidia,tegra30-slink
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  clocks:
26    items:
27      - description: module clock
28
29  resets:
30    items:
31      - description: module reset
32
33  reset-names:
34    items:
35      - const: spi
36
37  dmas:
38    items:
39      - description: DMA channel used for reception
40      - description: DMA channel used for transmission
41
42  dma-names:
43    items:
44      - const: rx
45      - const: tx
46
47  operating-points-v2:
48    $ref: /schemas/types.yaml#/definitions/phandle
49
50  power-domains:
51    items:
52      - description: phandle to the core power domain
53
54  spi-max-frequency:
55    description: Maximum SPI clocking speed of the controller in Hz.
56    $ref: /schemas/types.yaml#/definitions/uint32
57
58allOf:
59  - $ref: spi-controller.yaml
60
61unevaluatedProperties: false
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68  - resets
69  - reset-names
70  - dmas
71  - dma-names
72
73examples:
74  - |
75    #include <dt-bindings/clock/tegra20-car.h>
76    #include <dt-bindings/interrupt-controller/arm-gic.h>
77
78    spi@7000d600 {
79        compatible = "nvidia,tegra20-slink";
80        reg = <0x7000d600 0x200>;
81        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
82        spi-max-frequency = <25000000>;
83        #address-cells = <1>;
84        #size-cells = <0>;
85        clocks = <&tegra_car TEGRA20_CLK_SBC2>;
86        resets = <&tegra_car 44>;
87        reset-names = "spi";
88        dmas = <&apbdma 16>, <&apbdma 16>;
89        dma-names = "rx", "tx";
90    };
91