1*17a9ab02SThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*17a9ab02SThierry Reding%YAML 1.2 3*17a9ab02SThierry Reding--- 4*17a9ab02SThierry Reding$id: http://devicetree.org/schemas/spi/nvidia,tegra20-sflash.yaml# 5*17a9ab02SThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6*17a9ab02SThierry Reding 7*17a9ab02SThierry Redingtitle: NVIDIA Tegra20 SFLASH controller 8*17a9ab02SThierry Reding 9*17a9ab02SThierry Redingmaintainers: 10*17a9ab02SThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11*17a9ab02SThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12*17a9ab02SThierry Reding 13*17a9ab02SThierry Redingproperties: 14*17a9ab02SThierry Reding compatible: 15*17a9ab02SThierry Reding const: nvidia,tegra20-sflash 16*17a9ab02SThierry Reding 17*17a9ab02SThierry Reding reg: 18*17a9ab02SThierry Reding maxItems: 1 19*17a9ab02SThierry Reding 20*17a9ab02SThierry Reding interrupts: 21*17a9ab02SThierry Reding maxItems: 1 22*17a9ab02SThierry Reding 23*17a9ab02SThierry Reding clocks: 24*17a9ab02SThierry Reding items: 25*17a9ab02SThierry Reding - description: module clock 26*17a9ab02SThierry Reding 27*17a9ab02SThierry Reding resets: 28*17a9ab02SThierry Reding items: 29*17a9ab02SThierry Reding - description: module reset 30*17a9ab02SThierry Reding 31*17a9ab02SThierry Reding reset-names: 32*17a9ab02SThierry Reding items: 33*17a9ab02SThierry Reding - const: spi 34*17a9ab02SThierry Reding 35*17a9ab02SThierry Reding dmas: 36*17a9ab02SThierry Reding items: 37*17a9ab02SThierry Reding - description: DMA channel used for reception 38*17a9ab02SThierry Reding - description: DMA channel used for transmission 39*17a9ab02SThierry Reding 40*17a9ab02SThierry Reding dma-names: 41*17a9ab02SThierry Reding items: 42*17a9ab02SThierry Reding - const: rx 43*17a9ab02SThierry Reding - const: tx 44*17a9ab02SThierry Reding 45*17a9ab02SThierry Reding spi-max-frequency: 46*17a9ab02SThierry Reding description: Maximum SPI clocking speed of the controller in Hz. 47*17a9ab02SThierry Reding $ref: /schemas/types.yaml#/definitions/uint32 48*17a9ab02SThierry Reding 49*17a9ab02SThierry RedingallOf: 50*17a9ab02SThierry Reding - $ref: spi-controller.yaml 51*17a9ab02SThierry Reding 52*17a9ab02SThierry RedingunevaluatedProperties: false 53*17a9ab02SThierry Reding 54*17a9ab02SThierry Redingrequired: 55*17a9ab02SThierry Reding - compatible 56*17a9ab02SThierry Reding - reg 57*17a9ab02SThierry Reding - interrupts 58*17a9ab02SThierry Reding - clocks 59*17a9ab02SThierry Reding - resets 60*17a9ab02SThierry Reding - reset-names 61*17a9ab02SThierry Reding - dmas 62*17a9ab02SThierry Reding - dma-names 63*17a9ab02SThierry Reding 64*17a9ab02SThierry Redingexamples: 65*17a9ab02SThierry Reding - | 66*17a9ab02SThierry Reding #include <dt-bindings/clock/tegra20-car.h> 67*17a9ab02SThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 68*17a9ab02SThierry Reding 69*17a9ab02SThierry Reding spi@7000c380 { 70*17a9ab02SThierry Reding compatible = "nvidia,tegra20-sflash"; 71*17a9ab02SThierry Reding reg = <0x7000c380 0x80>; 72*17a9ab02SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 73*17a9ab02SThierry Reding spi-max-frequency = <25000000>; 74*17a9ab02SThierry Reding #address-cells = <1>; 75*17a9ab02SThierry Reding #size-cells = <0>; 76*17a9ab02SThierry Reding clocks = <&tegra_car TEGRA20_CLK_SPI>; 77*17a9ab02SThierry Reding resets = <&tegra_car 43>; 78*17a9ab02SThierry Reding reset-names = "spi"; 79*17a9ab02SThierry Reding dmas = <&apbdma 11>, <&apbdma 11>; 80*17a9ab02SThierry Reding dma-names = "rx", "tx"; 81*17a9ab02SThierry Reding }; 82