1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Serial NOR flash controller for MediaTek ARM SoCs
8
9maintainers:
10  - Bayi Cheng <bayi.cheng@mediatek.com>
11  - Chuanhong Guo <gch981213@gmail.com>
12
13description: |
14  This spi controller support single, dual, or quad mode transfer for
15  SPI NOR flash. There should be only one spi slave device following
16  generic spi bindings. It's not recommended to use this controller
17  for devices other than SPI NOR flash due to limited transfer
18  capability of this controller.
19
20allOf:
21  - $ref: /schemas/spi/spi-controller.yaml#
22
23properties:
24  compatible:
25    oneOf:
26      - items:
27          - enum:
28              - mediatek,mt2701-nor
29              - mediatek,mt2712-nor
30              - mediatek,mt7622-nor
31              - mediatek,mt7623-nor
32              - mediatek,mt7629-nor
33              - mediatek,mt8186-nor
34              - mediatek,mt8192-nor
35              - mediatek,mt8195-nor
36          - enum:
37              - mediatek,mt8173-nor
38      - items:
39          - const: mediatek,mt8173-nor
40  reg:
41    maxItems: 1
42
43  interrupts:
44    maxItems: 1
45
46  clocks:
47    minItems: 2
48    items:
49      - description: clock used for spi bus
50      - description: clock used for controller
51      - description: clock used for nor dma bus. this depends on hardware
52                     design, so this is optional.
53      - description: clock used for controller axi slave bus.
54                     this depends on hardware design, so it is optional.
55
56  clock-names:
57    minItems: 2
58    items:
59      - const: spi
60      - const: sf
61      - const: axi
62      - const: axi_s
63
64required:
65  - compatible
66  - reg
67  - interrupts
68  - clocks
69  - clock-names
70
71unevaluatedProperties: false
72
73examples:
74  - |
75    #include <dt-bindings/clock/mt8173-clk.h>
76
77    soc {
78      #address-cells = <2>;
79      #size-cells = <2>;
80
81      nor_flash: spi@1100d000 {
82        compatible = "mediatek,mt8173-nor";
83        reg = <0 0x1100d000 0 0xe0>;
84        interrupts = <1>;
85        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
86        clock-names = "spi", "sf";
87        #address-cells = <1>;
88        #size-cells = <0>;
89
90        flash@0 {
91          compatible = "jedec,spi-nor";
92          reg = <0>;
93        };
94      };
95    };
96