1*60edd652SLeilk Liu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*60edd652SLeilk Liu%YAML 1.2
3*60edd652SLeilk Liu---
4*60edd652SLeilk Liu$id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
5*60edd652SLeilk Liu$schema: http://devicetree.org/meta-schemas/core.yaml#
6*60edd652SLeilk Liu
7*60edd652SLeilk Liutitle: SPI Slave controller for MediaTek ARM SoCs
8*60edd652SLeilk Liu
9*60edd652SLeilk Liumaintainers:
10*60edd652SLeilk Liu  - Leilk Liu <leilk.liu@mediatek.com>
11*60edd652SLeilk Liu
12*60edd652SLeilk LiuallOf:
13*60edd652SLeilk Liu  - $ref: "/schemas/spi/spi-controller.yaml#"
14*60edd652SLeilk Liu
15*60edd652SLeilk Liuproperties:
16*60edd652SLeilk Liu  compatible:
17*60edd652SLeilk Liu    enum:
18*60edd652SLeilk Liu      - mediatek,mt2712-spi-slave
19*60edd652SLeilk Liu      - mediatek,mt8195-spi-slave
20*60edd652SLeilk Liu
21*60edd652SLeilk Liu  reg:
22*60edd652SLeilk Liu    maxItems: 1
23*60edd652SLeilk Liu
24*60edd652SLeilk Liu  interrupts:
25*60edd652SLeilk Liu    maxItems: 1
26*60edd652SLeilk Liu
27*60edd652SLeilk Liu  clocks:
28*60edd652SLeilk Liu    maxItems: 1
29*60edd652SLeilk Liu
30*60edd652SLeilk Liu  clock-names:
31*60edd652SLeilk Liu    items:
32*60edd652SLeilk Liu      - const: spi
33*60edd652SLeilk Liu
34*60edd652SLeilk Liurequired:
35*60edd652SLeilk Liu  - compatible
36*60edd652SLeilk Liu  - reg
37*60edd652SLeilk Liu  - interrupts
38*60edd652SLeilk Liu  - clocks
39*60edd652SLeilk Liu  - clock-names
40*60edd652SLeilk Liu
41*60edd652SLeilk LiuunevaluatedProperties: false
42*60edd652SLeilk Liu
43*60edd652SLeilk Liuexamples:
44*60edd652SLeilk Liu  - |
45*60edd652SLeilk Liu    #include <dt-bindings/clock/mt2712-clk.h>
46*60edd652SLeilk Liu    #include <dt-bindings/gpio/gpio.h>
47*60edd652SLeilk Liu    #include <dt-bindings/interrupt-controller/arm-gic.h>
48*60edd652SLeilk Liu    #include <dt-bindings/interrupt-controller/irq.h>
49*60edd652SLeilk Liu
50*60edd652SLeilk Liu    spi@10013000 {
51*60edd652SLeilk Liu      compatible = "mediatek,mt2712-spi-slave";
52*60edd652SLeilk Liu      reg = <0x10013000 0x100>;
53*60edd652SLeilk Liu      interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
54*60edd652SLeilk Liu      clocks = <&infracfg CLK_INFRA_AO_SPI1>;
55*60edd652SLeilk Liu      clock-names = "spi";
56*60edd652SLeilk Liu      assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
57*60edd652SLeilk Liu      assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
58*60edd652SLeilk Liu    };
59