1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence Quad SPI controller
8
9maintainers:
10  - Vaishnav Achath <vaishnav.a@ti.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: xlnx,versal-ospi-1.0
19    then:
20      required:
21        - power-domains
22  - if:
23      properties:
24        compatible:
25          contains:
26            const: starfive,jh7110-qspi
27    then:
28      properties:
29        resets:
30          minItems: 2
31          maxItems: 3
32
33        reset-names:
34          minItems: 2
35          maxItems: 3
36          items:
37            enum: [ qspi, qspi-ocp, rstc_ref ]
38
39    else:
40      properties:
41        resets:
42          maxItems: 2
43
44        reset-names:
45          minItems: 1
46          maxItems: 2
47          items:
48            enum: [ qspi, qspi-ocp ]
49  - if:
50      properties:
51        compatible:
52          contains:
53            const: amd,pensando-elba-qspi
54    then:
55      properties:
56        cdns,fifo-depth:
57          enum: [ 128, 256, 1024 ]
58          default: 1024
59    else:
60      properties:
61        cdns,fifo-depth:
62          enum: [ 128, 256 ]
63          default: 128
64
65properties:
66  compatible:
67    oneOf:
68      - items:
69          - enum:
70              - amd,pensando-elba-qspi
71              - ti,k2g-qspi
72              - ti,am654-ospi
73              - intel,lgm-qspi
74              - xlnx,versal-ospi-1.0
75              - intel,socfpga-qspi
76              - starfive,jh7110-qspi
77          - const: cdns,qspi-nor
78      - const: cdns,qspi-nor
79
80  reg:
81    items:
82      - description: the controller register set
83      - description: the controller data area
84
85  interrupts:
86    maxItems: 1
87
88  clocks:
89    maxItems: 1
90
91  cdns,fifo-depth:
92    description:
93      Size of the data FIFO in words.
94    $ref: /schemas/types.yaml#/definitions/uint32
95
96  cdns,fifo-width:
97    $ref: /schemas/types.yaml#/definitions/uint32
98    description:
99      Bus width of the data FIFO in bytes.
100    default: 4
101
102  cdns,trigger-address:
103    $ref: /schemas/types.yaml#/definitions/uint32
104    description:
105      32-bit indirect AHB trigger address.
106
107  cdns,is-decoded-cs:
108    type: boolean
109    description:
110      Flag to indicate whether decoder is used to select different chip select
111      for different memory regions.
112
113  cdns,rclk-en:
114    type: boolean
115    description:
116      Flag to indicate that QSPI return clock is used to latch the read
117      data rather than the QSPI clock. Make sure that QSPI return clock
118      is populated on the board before using this property.
119
120  power-domains:
121    maxItems: 1
122
123  resets:
124    minItems: 2
125    maxItems: 3
126
127  reset-names:
128    minItems: 2
129    maxItems: 3
130    items:
131      enum: [ qspi, qspi-ocp, rstc_ref ]
132
133required:
134  - compatible
135  - reg
136  - interrupts
137  - clocks
138  - cdns,fifo-depth
139  - cdns,fifo-width
140  - cdns,trigger-address
141  - '#address-cells'
142  - '#size-cells'
143
144unevaluatedProperties: false
145
146examples:
147  - |
148    qspi: spi@ff705000 {
149        compatible = "cdns,qspi-nor";
150        #address-cells = <1>;
151        #size-cells = <0>;
152        reg = <0xff705000 0x1000>,
153              <0xffa00000 0x1000>;
154        interrupts = <0 151 4>;
155        clocks = <&qspi_clk>;
156        cdns,fifo-depth = <128>;
157        cdns,fifo-width = <4>;
158        cdns,trigger-address = <0x00000000>;
159        resets = <&rst 0x1>, <&rst 0x2>;
160        reset-names = "qspi", "qspi-ocp";
161
162        flash@0 {
163            compatible = "jedec,spi-nor";
164            reg = <0x0>;
165        };
166    };
167