1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence Quad SPI controller
8
9maintainers:
10  - Pratyush Yadav <p.yadav@ti.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: xlnx,versal-ospi-1.0
19    then:
20      required:
21        - power-domains
22
23properties:
24  compatible:
25    oneOf:
26      - items:
27          - enum:
28              - ti,k2g-qspi
29              - ti,am654-ospi
30              - intel,lgm-qspi
31              - xlnx,versal-ospi-1.0
32          - const: cdns,qspi-nor
33      - const: cdns,qspi-nor
34
35  reg:
36    items:
37      - description: the controller register set
38      - description: the controller data area
39
40  interrupts:
41    maxItems: 1
42
43  clocks:
44    maxItems: 1
45
46  cdns,fifo-depth:
47    description:
48      Size of the data FIFO in words.
49    $ref: "/schemas/types.yaml#/definitions/uint32"
50    enum: [ 128, 256 ]
51    default: 128
52
53  cdns,fifo-width:
54    $ref: /schemas/types.yaml#/definitions/uint32
55    description:
56      Bus width of the data FIFO in bytes.
57    default: 4
58
59  cdns,trigger-address:
60    $ref: /schemas/types.yaml#/definitions/uint32
61    description:
62      32-bit indirect AHB trigger address.
63
64  cdns,is-decoded-cs:
65    type: boolean
66    description:
67      Flag to indicate whether decoder is used to select different chip select
68      for different memory regions.
69
70  cdns,rclk-en:
71    type: boolean
72    description:
73      Flag to indicate that QSPI return clock is used to latch the read
74      data rather than the QSPI clock. Make sure that QSPI return clock
75      is populated on the board before using this property.
76
77  power-domains:
78    maxItems: 1
79
80  resets:
81    maxItems: 2
82
83  reset-names:
84    minItems: 1
85    maxItems: 2
86    items:
87      enum: [ qspi, qspi-ocp ]
88
89# subnode's properties
90patternProperties:
91  "@[0-9a-f]+$":
92    type: object
93    description:
94      Flash device uses the below defined properties in the subnode.
95
96    properties:
97      cdns,read-delay:
98        $ref: /schemas/types.yaml#/definitions/uint32
99        description:
100          Delay for read capture logic, in clock cycles.
101
102      cdns,tshsl-ns:
103        description:
104          Delay in nanoseconds for the length that the master mode chip select
105          outputs are de-asserted between transactions.
106
107      cdns,tsd2d-ns:
108        description:
109          Delay in nanoseconds between one chip select being de-activated
110          and the activation of another.
111
112      cdns,tchsh-ns:
113        description:
114          Delay in nanoseconds between last bit of current transaction and
115          deasserting the device chip select (qspi_n_ss_out).
116
117      cdns,tslch-ns:
118        description:
119          Delay in nanoseconds between setting qspi_n_ss_out low and
120          first bit transfer.
121
122required:
123  - compatible
124  - reg
125  - interrupts
126  - clocks
127  - cdns,fifo-depth
128  - cdns,fifo-width
129  - cdns,trigger-address
130  - '#address-cells'
131  - '#size-cells'
132
133unevaluatedProperties: false
134
135examples:
136  - |
137    qspi: spi@ff705000 {
138      compatible = "cdns,qspi-nor";
139      #address-cells = <1>;
140      #size-cells = <0>;
141      reg = <0xff705000 0x1000>,
142            <0xffa00000 0x1000>;
143      interrupts = <0 151 4>;
144      clocks = <&qspi_clk>;
145      cdns,fifo-depth = <128>;
146      cdns,fifo-width = <4>;
147      cdns,trigger-address = <0x00000000>;
148      resets = <&rst 0x1>, <&rst 0x2>;
149      reset-names = "qspi", "qspi-ocp";
150
151      flash@0 {
152              compatible = "jedec,spi-nor";
153              reg = <0x0>;
154      };
155    };
156