1f8043872SChris BootBroadcom BCM2835 SPI0 controller 2f8043872SChris Boot 3f8043872SChris BootThe BCM2835 contains two forms of SPI master controller, one known simply as 4f8043872SChris BootSPI0, and the other known as the "Universal SPI Master"; part of the 5f8043872SChris Bootauxilliary block. This binding applies to the SPI0 controller. 6f8043872SChris Boot 7f8043872SChris BootRequired properties: 8f8043872SChris Boot- compatible: Should be "brcm,bcm2835-spi". 9f8043872SChris Boot- reg: Should contain register location and length. 10f8043872SChris Boot- interrupts: Should contain interrupt. 11f8043872SChris Boot- clocks: The clock feeding the SPI controller. 12f8043872SChris Boot 13f8043872SChris BootExample: 14f8043872SChris Boot 15f8043872SChris Bootspi@20204000 { 16f8043872SChris Boot compatible = "brcm,bcm2835-spi"; 17f8043872SChris Boot reg = <0x7e204000 0x1000>; 18f8043872SChris Boot interrupts = <2 22>; 19f8043872SChris Boot clocks = <&clk_spi>; 20f8043872SChris Boot #address-cells = <1>; 21f8043872SChris Boot #size-cells = <0>; 22f8043872SChris Boot}; 23