1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Atmel SPI device 9 10maintainers: 11 - Tudor Ambarus <tudor.ambarus@linaro.org> 12 13allOf: 14 - $ref: spi-controller.yaml# 15 16properties: 17 compatible: 18 oneOf: 19 - const: atmel,at91rm9200-spi 20 - items: 21 - const: microchip,sam9x60-spi 22 - const: atmel,at91rm9200-spi 23 - items: 24 - const: microchip,sam9x7-spi 25 - const: microchip,sam9x60-spi 26 - const: atmel,at91rm9200-spi 27 28 reg: 29 maxItems: 1 30 31 interrupts: 32 maxItems: 1 33 34 clock-names: 35 contains: 36 const: spi_clk 37 38 clocks: 39 maxItems: 1 40 41 dmas: 42 items: 43 - description: TX DMA Channel 44 - description: RX DMA Channel 45 46 dma-names: 47 items: 48 - const: tx 49 - const: rx 50 51 atmel,fifo-size: 52 $ref: /schemas/types.yaml#/definitions/uint32 53 description: | 54 Maximum number of data the RX and TX FIFOs can store for FIFO 55 capable SPI controllers. 56 enum: [ 16, 32 ] 57 58required: 59 - compatible 60 - reg 61 - interrupts 62 - clock-names 63 - clocks 64 65unevaluatedProperties: false 66 67examples: 68 - | 69 #include <dt-bindings/gpio/gpio.h> 70 #include <dt-bindings/interrupt-controller/irq.h> 71 72 spi1: spi@fffcc000 { 73 compatible = "atmel,at91rm9200-spi"; 74 reg = <0xfffcc000 0x4000>; 75 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 clocks = <&spi1_clk>; 79 clock-names = "spi_clk"; 80 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; 81 atmel,fifo-size = <32>; 82 83 mmc@0 { 84 compatible = "mmc-spi-slot"; 85 reg = <0>; 86 gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */ 87 spi-max-frequency = <25000000>; 88 }; 89 }; 90