1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Amlogic Meson SPI Communication Controller
9
10maintainers:
11  - Neil Armstrong <narmstrong@baylibre.com>
12
13allOf:
14  - $ref: "spi-controller.yaml#"
15
16description: |
17  The Meson SPICC is a generic SPI controller for general purpose Full-Duplex
18  communications with dedicated 16 words RX/TX PIO FIFOs.
19
20properties:
21  compatible:
22    enum:
23      - amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs
24      - amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs
25      - amlogic,meson-g12a-spicc # SPICC controller on Amlogic G12A and compatible SoCs
26
27  interrupts:
28    maxItems: 1
29
30  reg:
31    maxItems: 1
32
33  resets:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  clock-names:
40    description: input clock for the baud rate generator
41    items:
42      - const: core
43
44if:
45  properties:
46    compatible:
47      contains:
48        enum:
49          - amlogic,meson-g12a-spicc
50
51then:
52  properties:
53    clocks:
54      contains:
55        items:
56          - description: controller register bus clock
57          - description: baud rate generator and delay control clock
58
59    clock-names:
60      minItems: 2
61      items:
62        - const: core
63        - const: pclk
64
65required:
66  - compatible
67  - reg
68  - interrupts
69  - clocks
70  - clock-names
71
72examples:
73  - |
74    spi@c1108d80 {
75          compatible = "amlogic,meson-gx-spicc";
76          reg = <0xc1108d80 0x80>;
77          interrupts = <112>;
78          clocks = <&clk81>;
79          clock-names = "core";
80          #address-cells = <1>;
81          #size-cells = <0>;
82
83          ethernet-switch@0 {
84              compatible = "micrel,ks8995m";
85              spi-max-frequency = <1000000>;
86              reg = <0>;
87          };
88    };
89
90