12f00f771SMaruthi Srinivas BayyavarapuDevice-Tree bindings for Xilinx SPDIF IP 22f00f771SMaruthi Srinivas Bayyavarapu 32f00f771SMaruthi Srinivas BayyavarapuThe IP supports playback and capture of SPDIF audio 42f00f771SMaruthi Srinivas Bayyavarapu 52f00f771SMaruthi Srinivas BayyavarapuRequired properties: 62f00f771SMaruthi Srinivas Bayyavarapu - compatible: "xlnx,spdif-2.0" 72f00f771SMaruthi Srinivas Bayyavarapu - clock-names: List of input clocks. 82f00f771SMaruthi Srinivas Bayyavarapu Required elements: "s_axi_aclk", "aud_clk_i" 92f00f771SMaruthi Srinivas Bayyavarapu - clocks: Input clock specifier. Refer to common clock bindings. 102f00f771SMaruthi Srinivas Bayyavarapu - reg: Base address and address length of the IP core instance. 112f00f771SMaruthi Srinivas Bayyavarapu - interrupts-parent: Phandle for interrupt controller. 122f00f771SMaruthi Srinivas Bayyavarapu - interrupts: List of Interrupt numbers. 132f00f771SMaruthi Srinivas Bayyavarapu - xlnx,spdif-mode: 0 :- receiver mode 142f00f771SMaruthi Srinivas Bayyavarapu 1 :- transmitter mode 152f00f771SMaruthi Srinivas Bayyavarapu - xlnx,aud_clk_i: input audio clock value. 162f00f771SMaruthi Srinivas Bayyavarapu 172f00f771SMaruthi Srinivas BayyavarapuExample: 182f00f771SMaruthi Srinivas Bayyavarapu spdif_0: spdif@80010000 { 192f00f771SMaruthi Srinivas Bayyavarapu clock-names = "aud_clk_i", "s_axi_aclk"; 202f00f771SMaruthi Srinivas Bayyavarapu clocks = <&misc_clk_0>, <&clk 71>; 212f00f771SMaruthi Srinivas Bayyavarapu compatible = "xlnx,spdif-2.0"; 222f00f771SMaruthi Srinivas Bayyavarapu interrupt-names = "spdif_interrupt"; 232f00f771SMaruthi Srinivas Bayyavarapu interrupt-parent = <&gic>; 242f00f771SMaruthi Srinivas Bayyavarapu interrupts = <0 91 4>; 252f00f771SMaruthi Srinivas Bayyavarapu reg = <0x0 0x80010000 0x0 0x10000>; 262f00f771SMaruthi Srinivas Bayyavarapu xlnx,spdif-mode = <1>; 272f00f771SMaruthi Srinivas Bayyavarapu xlnx,aud_clk_i = <49152913>; 282f00f771SMaruthi Srinivas Bayyavarapu }; 29