1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
9
10maintainers:
11  - Dan Murphy <dmurphy@ti.com>
12
13description: |
14  The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15  PDM microphones recording), high-performance audio, analog-to-digital
16  converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
17  family supports line and  microphone Inputs, and offers a programmable
18  microphone bias or supply voltage generation.
19
20  Specifications can be found at:
21    https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
22    https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
23    https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf
24
25properties:
26  compatible:
27    oneOf:
28      - const: ti,tlv320adc3140
29      - const: ti,tlv320adc5140
30      - const: ti,tlv320adc6140
31
32  reg:
33    maxItems: 1
34    description: |
35      I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
36
37  reset-gpios:
38    description: |
39      GPIO used for hardware reset.
40
41  areg-supply:
42    description: |
43      Regulator with AVDD at 3.3V.  If not defined then the internal regulator
44      is enabled.
45
46  ti,mic-bias-source:
47    description: |
48      Indicates the source for MIC Bias.
49      0 - Mic bias is set to VREF
50      1 - Mic bias is set to VREF × 1.096
51      6 - Mic bias is set to AVDD
52    $ref: /schemas/types.yaml#/definitions/uint32
53    enum: [0, 1, 6]
54
55  ti,vref-source:
56    description: |
57      Indicates the source for MIC Bias.
58      0 - Set VREF to 2.75V
59      1 - Set VREF to 2.5V
60      2 - Set VREF to 1.375V
61    $ref: /schemas/types.yaml#/definitions/uint32
62    enum: [0, 1, 2]
63
64  ti,pdm-edge-select:
65    description: |
66       Defines the PDMCLK sampling edge configuration for the PDM inputs.  This
67       array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.
68
69       0 - (default) Odd channel is latched on the negative edge and even
70       channel is latched on the the positive edge.
71       1 - Odd channel is latched on the positive edge and even channel is
72       latched on the the negative edge.
73
74       PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
75       PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
76       PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
77       PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
78
79    $ref: /schemas/types.yaml#/definitions/uint32-array
80    minItems: 1
81    maxItems: 4
82    items:
83      maximum: 1
84    default: [0, 0, 0, 0]
85
86  ti,gpi-config:
87    description: |
88       Defines the configuration for the general purpose input pins (GPI).
89       The array is defined as <GPI1 GPI2 GPI3 GPI4>.
90
91       0 - (default) disabled
92       1 - GPIX is configured as a general-purpose input (GPI)
93       2 - GPIX is configured as a master clock input (MCLK)
94       3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
95       4 - GPIX is configured as a PDM data input for channel 1 and channel
96            (PDMDIN1)
97       5 - GPIX is configured as a PDM data input for channel 3 and channel
98            (PDMDIN2)
99       6 - GPIX is configured as a PDM data input for channel 5 and channel
100            (PDMDIN3)
101       7 - GPIX is configured as a PDM data input for channel 7 and channel
102            (PDMDIN4)
103
104    $ref: /schemas/types.yaml#/definitions/uint32-array
105    minItems: 1
106    maxItems: 4
107    items:
108      maximum: 7
109    default: [0, 0, 0, 0]
110
111  ti,asi-tx-drive:
112    type: boolean
113    description: |
114      When set the device will set the Tx ASI output to a Hi-Z state for unused
115      data cycles. Default is to drive the output low on unused ASI cycles.
116
117patternProperties:
118  '^ti,gpo-config-[1-4]$':
119    $ref: /schemas/types.yaml#/definitions/uint32-array
120    description: |
121       Defines the configuration and output driver for the general purpose
122       output pins (GPO).  These values are pairs, the first value is for the
123       configuration type and the second value is for the output drive type.
124       The array is defined as <GPO_CFG GPO_DRV>
125
126       GPO output configuration can be one of the following:
127
128       0 - (default) disabled
129       1 - GPOX is configured as a general-purpose output (GPO)
130       2 - GPOX is configured as a device interrupt output (IRQ)
131       3 - GPOX is configured as a secondary ASI output (SDOUT2)
132       4 - GPOX is configured as a PDM clock output (PDMCLK)
133
134       GPO output drive configuration for the GPO pins can be one of the following:
135
136       0d - (default) Hi-Z output
137       1d - Drive active low and active high
138       2d - Drive active low and weak high
139       3d - Drive active low and Hi-Z
140       4d - Drive weak low and active high
141       5d - Drive Hi-Z and active high
142
143  ti,gpio-config:
144    description: |
145       Defines the configuration and output drive for the General Purpose
146       Input and Output pin (GPIO1). Its value is a pair, the first value is for
147       the configuration type and the second value is for the output drive
148       type. The array is defined as <GPIO1_CFG GPIO1_DRV>
149
150       configuration for the GPIO pin can be one of the following:
151       0 - disabled
152       1 - GPIO1 is configured as a general-purpose output (GPO)
153       2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
154       3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
155       4 - GPIO1 is configured as a PDM clock output (PDMCLK)
156       8 - GPIO1 is configured as an input to control when MICBIAS turns on or
157           off (MICBIAS_EN)
158       9 - GPIO1 is configured as a general-purpose input (GPI)
159       10 - GPIO1 is configured as a master clock input (MCLK)
160       11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
161       12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
162            (PDMDIN1)
163       13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
164            (PDMDIN2)
165       14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
166            (PDMDIN3)
167       15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
168            (PDMDIN4)
169
170       output drive type for the GPIO pin can be one of the following:
171       0 - Hi-Z output
172       1 - Drive active low and active high
173       2 - (default) Drive active low and weak high
174       3 - Drive active low and Hi-Z
175       4 - Drive weak low and active high
176       5 - Drive Hi-Z and active high
177
178    allOf:
179      - $ref: /schemas/types.yaml#/definitions/uint32-array
180      - minItems: 2
181        maxItems: 2
182        items:
183          maximum: 15
184        default: [2, 2]
185
186required:
187  - compatible
188  - reg
189
190additionalProperties: false
191
192examples:
193  - |
194    #include <dt-bindings/gpio/gpio.h>
195    i2c0 {
196      #address-cells = <1>;
197      #size-cells = <0>;
198      codec: codec@4c {
199        compatible = "ti,tlv320adc5140";
200        reg = <0x4c>;
201        ti,mic-bias-source = <6>;
202        ti,pdm-edge-select = <0 1 0 1>;
203        ti,gpi-config = <4 5 6 7>;
204        ti,gpio-config = <10 2>;
205        ti,gpo-config-1 = <0 0>;
206        ti,gpo-config-2 = <0 0>;
207        reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
208      };
209    };
210