1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12allOf:
13  - $ref: dai-common.yaml#
14
15properties:
16  compatible:
17    items:
18      - enum:
19          - renesas,r9a07g043-ssi  # RZ/G2UL
20          - renesas,r9a07g044-ssi  # RZ/G2{L,LC}
21          - renesas,r9a07g054-ssi  # RZ/V2L
22      - const: renesas,rz-ssi
23
24  reg:
25    maxItems: 1
26
27  interrupts:
28    maxItems: 4
29
30  interrupt-names:
31    items:
32      - const: int_req
33      - const: dma_rx
34      - const: dma_tx
35      - const: dma_rt
36
37  clocks:
38    maxItems: 4
39
40  clock-names:
41    items:
42      - const: ssi
43      - const: ssi_sfr
44      - const: audio_clk1
45      - const: audio_clk2
46
47  power-domains:
48    maxItems: 1
49
50  resets:
51    maxItems: 1
52
53  dmas:
54    minItems: 1
55    maxItems: 2
56    description:
57      The first cell represents a phandle to dmac.
58      The second cell specifies the encoded MID/RID values of the SSI port
59      connected to the DMA client and the slave channel configuration
60      parameters.
61      bits[0:9]   - Specifies MID/RID value of a SSI channel as below
62                    MID/RID value of SSI rx0 = 0x256
63                    MID/RID value of SSI tx0 = 0x255
64                    MID/RID value of SSI rx1 = 0x25a
65                    MID/RID value of SSI tx1 = 0x259
66                    MID/RID value of SSI rt2 = 0x25f
67                    MID/RID value of SSI rx3 = 0x262
68                    MID/RID value of SSI tx3 = 0x261
69      bit[10]     - HIEN = 1, Detects a request in response to the rising edge
70                    of the signal
71      bit[11]     - LVL = 0, Detects based on the edge
72      bits[12:14] - AM = 2, Bus cycle mode
73      bit[15]     - TM = 0, Single transfer mode
74
75  dma-names:
76    oneOf:
77      - items:
78          - const: tx
79          - const: rx
80      - items:
81          - const: rt
82
83  '#sound-dai-cells':
84    const: 0
85
86required:
87  - compatible
88  - reg
89  - interrupts
90  - interrupt-names
91  - clocks
92  - clock-names
93  - resets
94  - '#sound-dai-cells'
95
96unevaluatedProperties: false
97
98examples:
99  - |
100    #include <dt-bindings/interrupt-controller/arm-gic.h>
101    #include <dt-bindings/clock/r9a07g044-cpg.h>
102
103    ssi0: ssi@10049c00 {
104        compatible = "renesas,r9a07g044-ssi",
105                     "renesas,rz-ssi";
106            reg = <0x10049c00 0x400>;
107            interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
108                         <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
109                         <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
110                         <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
111            interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
112            clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
113                     <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
114                     <&audio_clk1>,
115                     <&audio_clk2>;
116            clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
117            power-domains = <&cpg>;
118            resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
119            dmas = <&dmac 0x2655>,
120                   <&dmac 0x2656>;
121            dma-names = "tx", "rx";
122            #sound-dai-cells = <0>;
123    };
124