1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Tegra210 AHUB Device Tree Bindings
8
9description: |
10  The Audio Hub (AHUB) comprises a collection of hardware accelerators
11  for audio pre-processing, post-processing and a programmable full
12  crossbar for routing audio data across these accelerators. It has
13  external interfaces such as I2S, DMIC, DSPK. It interfaces with ADMA
14  engine through ADMAIF.
15
16maintainers:
17  - Jon Hunter <jonathanh@nvidia.com>
18  - Sameer Pujar <spujar@nvidia.com>
19
20properties:
21  $nodename:
22    pattern: "^ahub@[0-9a-f]*$"
23
24  compatible:
25    oneOf:
26      - enum:
27          - nvidia,tegra210-ahub
28          - nvidia,tegra186-ahub
29      - items:
30          - const: nvidia,tegra194-ahub
31          - const: nvidia,tegra186-ahub
32
33  reg:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  clock-names:
40    const: ahub
41
42  assigned-clocks:
43    maxItems: 1
44
45  assigned-clock-parents:
46    maxItems: 1
47
48  assigned-clock-rates:
49    maxItems: 1
50
51  "#address-cells":
52    const: 1
53
54  "#size-cells":
55    const: 1
56
57  ranges: true
58
59required:
60  - compatible
61  - reg
62  - clocks
63  - clock-names
64  - assigned-clocks
65  - assigned-clock-parents
66  - "#address-cells"
67  - "#size-cells"
68  - ranges
69
70additionalProperties:
71  type: object
72
73examples:
74  - |
75    #include<dt-bindings/clock/tegra210-car.h>
76
77    ahub@702d0800 {
78        compatible = "nvidia,tegra210-ahub";
79        reg = <0x702d0800 0x800>;
80        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
81        clock-names = "ahub";
82        assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
83        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
84        #address-cells = <1>;
85        #size-cells = <1>;
86        ranges = <0x702d0000 0x702d0000 0x0000e400>;
87
88        // All AHUB child nodes below
89        admaif@702d0000 {
90            compatible = "nvidia,tegra210-admaif";
91            reg = <0x702d0000 0x800>;
92            dmas = <&adma 1>,  <&adma 1>,
93               <&adma 2>,  <&adma 2>,
94               <&adma 3>,  <&adma 3>,
95               <&adma 4>,  <&adma 4>,
96               <&adma 5>,  <&adma 5>,
97               <&adma 6>,  <&adma 6>,
98               <&adma 7>,  <&adma 7>,
99               <&adma 8>,  <&adma 8>,
100               <&adma 9>,  <&adma 9>,
101               <&adma 10>, <&adma 10>;
102            dma-names = "rx1",  "tx1",
103                    "rx2",  "tx2",
104                    "rx3",  "tx3",
105                    "rx4",  "tx4",
106                    "rx5",  "tx5",
107                    "rx6",  "tx6",
108                    "rx7",  "tx7",
109                    "rx8",  "tx8",
110                    "rx9",  "tx9",
111                    "rx10", "tx10";
112        };
113
114        i2s@702d1000 {
115            compatible = "nvidia,tegra210-i2s";
116            reg = <0x702d1000 0x100>;
117            clocks = <&tegra_car TEGRA210_CLK_I2S0>;
118            clock-names = "i2s";
119            assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
120            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
121            assigned-clock-rates = <1536000>;
122            sound-name-prefix = "I2S1";
123        };
124
125        dmic@702d4000 {
126            compatible = "nvidia,tegra210-dmic";
127            reg = <0x702d4000 0x100>;
128            clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
129            clock-names = "dmic";
130            assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
131            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
132            assigned-clock-rates = <3072000>;
133            sound-name-prefix = "DMIC1";
134        };
135
136        // More child nodes to follow
137    };
138
139...
140