1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra20 S/PDIF Controller
8
9description: |
10  The S/PDIF controller supports both input and output in serial audio
11  digital interface format. The input controller can digitally recover
12  a clock from the received stream. The S/PDIF controller is also used
13  to generate the embedded audio for HDMI output channel.
14
15maintainers:
16  - Thierry Reding <treding@nvidia.com>
17  - Jon Hunter <jonathanh@nvidia.com>
18
19properties:
20  compatible:
21    const: nvidia,tegra20-spdif
22
23  reg:
24    maxItems: 1
25
26  resets:
27    maxItems: 1
28
29  interrupts:
30    maxItems: 1
31
32  clocks:
33    minItems: 2
34
35  clock-names:
36    items:
37      - const: out
38      - const: in
39
40  dmas:
41    minItems: 2
42
43  dma-names:
44    items:
45      - const: rx
46      - const: tx
47
48  "#sound-dai-cells":
49    const: 0
50
51  nvidia,fixed-parent-rate:
52    description: |
53      Specifies whether board prefers parent clock to stay at a fixed rate.
54      This allows multiple Tegra20 audio components work simultaneously by
55      limiting number of supportable audio rates.
56    type: boolean
57
58required:
59  - compatible
60  - reg
61  - resets
62  - interrupts
63  - clocks
64  - clock-names
65  - dmas
66  - dma-names
67  - "#sound-dai-cells"
68
69additionalProperties: false
70
71examples:
72  - |
73    spdif@70002400 {
74        compatible = "nvidia,tegra20-spdif";
75        reg = <0x70002400 0x200>;
76        interrupts = <77>;
77        clocks = <&clk 99>, <&clk 98>;
78        clock-names = "out", "in";
79        resets = <&rst 10>;
80        dmas = <&apbdma 3>, <&apbdma 3>;
81        dma-names = "rx", "tx";
82        #sound-dai-cells = <0>;
83    };
84
85...
86