1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek AFE PCM controller for mt8195
8
9maintainers:
10  - Trevor Wu <trevor.wu@mediatek.com>
11
12properties:
13  compatible:
14    const: mediatek,mt8195-audio
15
16  reg:
17    maxItems: 1
18
19  interrupts:
20    maxItems: 1
21
22  memory-region:
23    maxItems: 1
24    description: |
25      Shared memory region for AFE memif.  A "shared-dma-pool".
26      See ../reserved-memory/reserved-memory.txt for details.
27
28  mediatek,topckgen:
29    $ref: "/schemas/types.yaml#/definitions/phandle"
30    description: The phandle of the mediatek topckgen controller
31
32  power-domains:
33    maxItems: 1
34
35  clocks:
36    items:
37      - description: 26M clock
38      - description: audio pll1 clock
39      - description: audio pll2 clock
40      - description: clock divider for i2si1_mck
41      - description: clock divider for i2si2_mck
42      - description: clock divider for i2so1_mck
43      - description: clock divider for i2so2_mck
44      - description: clock divider for dptx_mck
45      - description: a1sys hoping clock
46      - description: audio intbus clock
47      - description: audio hires clock
48      - description: audio local bus clock
49      - description: mux for dptx_mck
50      - description: mux for i2so1_mck
51      - description: mux for i2so2_mck
52      - description: mux for i2si1_mck
53      - description: mux for i2si2_mck
54      - description: audio infra 26M clock
55      - description: infra bus clock
56
57  clock-names:
58    items:
59      - const: clk26m
60      - const: apll1_ck
61      - const: apll2_ck
62      - const: apll12_div0
63      - const: apll12_div1
64      - const: apll12_div2
65      - const: apll12_div3
66      - const: apll12_div9
67      - const: a1sys_hp_sel
68      - const: aud_intbus_sel
69      - const: audio_h_sel
70      - const: audio_local_bus_sel
71      - const: dptx_m_sel
72      - const: i2so1_m_sel
73      - const: i2so2_m_sel
74      - const: i2si1_m_sel
75      - const: i2si2_m_sel
76      - const: infra_ao_audio_26m_b
77      - const: scp_adsp_audiodsp
78
79  mediatek,etdm-in1-chn-disabled:
80    $ref: /schemas/types.yaml#/definitions/uint8-array
81    maxItems: 24
82    description: Specify which input channel should be disabled.
83
84  mediatek,etdm-in2-chn-disabled:
85    $ref: /schemas/types.yaml#/definitions/uint8-array
86    maxItems: 16
87    description: Specify which input channel should be disabled.
88
89patternProperties:
90  "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
91    description: Specify etdm in mclk output rate for always on case.
92
93  "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
94    description: Specify etdm out mclk output rate for always on case.
95
96  "^mediatek,etdm-in[1-2]-multi-pin-mode$":
97    type: boolean
98    description: if present, the etdm data mode is I2S.
99
100  "^mediatek,etdm-out[1-3]-multi-pin-mode$":
101    type: boolean
102    description: if present, the etdm data mode is I2S.
103
104  "^mediatek,etdm-in[1-2]-cowork-source$":
105    $ref: /schemas/types.yaml#/definitions/uint32
106    description: |
107      etdm modules can share the same external clock pin. Specify
108      which etdm clock source is required by this etdm in moudule.
109    enum:
110      - 0 # etdm1_in
111      - 1 # etdm2_in
112      - 2 # etdm1_out
113      - 3 # etdm2_out
114
115  "^mediatek,etdm-out[1-2]-cowork-source$":
116    $ref: /schemas/types.yaml#/definitions/uint32
117    description: |
118      etdm modules can share the same external clock pin. Specify
119      which etdm clock source is required by this etdm out moudule.
120    enum:
121      - 0 # etdm1_in
122      - 1 # etdm2_in
123      - 2 # etdm1_out
124      - 3 # etdm2_out
125
126required:
127  - compatible
128  - reg
129  - interrupts
130  - mediatek,topckgen
131  - power-domains
132  - clocks
133  - clock-names
134  - memory-region
135
136additionalProperties: false
137
138examples:
139  - |
140    #include <dt-bindings/interrupt-controller/arm-gic.h>
141    #include <dt-bindings/interrupt-controller/irq.h>
142
143    afe: mt8195-afe-pcm@10890000 {
144        compatible = "mediatek,mt8195-audio";
145        reg = <0x10890000 0x10000>;
146        interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
147        mediatek,topckgen = <&topckgen>;
148        power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO
149        memory-region = <&snd_dma_mem_reserved>;
150        clocks = <&clk26m>,
151                 <&topckgen 163>, //CLK_TOP_APLL1
152                 <&topckgen 166>, //CLK_TOP_APLL2
153                 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
154                 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
155                 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
156                 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
157                 <&topckgen 238>, //CLK_TOP_APLL12_DIV9
158                 <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL
159                 <&topckgen 33>, //CLK_TOP_AUD_INTBUS_SEL
160                 <&topckgen 34>, //CLK_TOP_AUDIO_H_SEL
161                 <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS_SEL
162                 <&topckgen 98>, //CLK_TOP_DPTX_M_SEL
163                 <&topckgen 94>, //CLK_TOP_I2SO1_M_SEL
164                 <&topckgen 95>, //CLK_TOP_I2SO2_M_SEL
165                 <&topckgen 96>, //CLK_TOP_I2SI1_M_SEL
166                 <&topckgen 97>, //CLK_TOP_I2SI2_M_SEL
167                 <&infracfg_ao 50>, //CLK_INFRA_AO_AUDIO_26M_B
168                 <&scp_adsp 0>; //CLK_SCP_ADSP_AUDIODSP
169        clock-names = "clk26m",
170                      "apll1_ck",
171                      "apll2_ck",
172                      "apll12_div0",
173                      "apll12_div1",
174                      "apll12_div2",
175                      "apll12_div3",
176                      "apll12_div9",
177                      "a1sys_hp_sel",
178                      "aud_intbus_sel",
179                      "audio_h_sel",
180                      "audio_local_bus_sel",
181                      "dptx_m_sel",
182                      "i2so1_m_sel",
183                      "i2so2_m_sel",
184                      "i2si1_m_sel",
185                      "i2si2_m_sel",
186                      "infra_ao_audio_26m_b",
187                      "scp_adsp_audiodsp";
188    };
189
190...
191