1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek AFE PCM controller for mt8192
8
9maintainers:
10  - Jiaxin Yu <jiaxin.yu@mediatek.com>
11  - Shane Chien <shane.chien@mediatek.com>
12
13properties:
14  compatible:
15    const: mediatek,mt8192-audio
16
17  interrupts:
18    maxItems: 1
19
20  resets:
21    maxItems: 1
22
23  reset-names:
24    const: audiosys
25
26  mediatek,apmixedsys:
27    $ref: "/schemas/types.yaml#/definitions/phandle"
28    description: The phandle of the mediatek apmixedsys controller
29
30  mediatek,infracfg:
31    $ref: "/schemas/types.yaml#/definitions/phandle"
32    description: The phandle of the mediatek infracfg controller
33
34  mediatek,topckgen:
35    $ref: "/schemas/types.yaml#/definitions/phandle"
36    description: The phandle of the mediatek topckgen controller
37
38  power-domains:
39    maxItems: 1
40
41  clocks:
42    items:
43      - description: AFE clock
44      - description: ADDA DAC clock
45      - description: ADDA DAC pre-distortion clock
46      - description: audio infra sys clock
47      - description: audio infra 26M clock
48
49  clock-names:
50    items:
51      - const: aud_afe_clk
52      - const: aud_dac_clk
53      - const: aud_dac_predis_clk
54      - const: aud_infra_clk
55      - const: aud_infra_26m_clk
56
57patternProperties:
58  "^i2s[0-35-9]-share$":
59    description: Name of the I2S bus that is shared with this bus
60    pattern: "^I2S[0-35-9]$"
61
62required:
63  - compatible
64  - interrupts
65  - resets
66  - reset-names
67  - mediatek,apmixedsys
68  - mediatek,infracfg
69  - mediatek,topckgen
70  - power-domains
71  - clocks
72  - clock-names
73
74additionalProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/clock/mt8192-clk.h>
79    #include <dt-bindings/interrupt-controller/arm-gic.h>
80    #include <dt-bindings/interrupt-controller/irq.h>
81    #include <dt-bindings/power/mt8192-power.h>
82    #include <dt-bindings/reset/mt8192-resets.h>
83
84    afe: mt8192-afe-pcm {
85        compatible = "mediatek,mt8192-audio";
86        interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
87        resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
88        reset-names = "audiosys";
89        mediatek,apmixedsys = <&apmixedsys>;
90        mediatek,infracfg = <&infracfg>;
91        mediatek,topckgen = <&topckgen>;
92        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
93        clocks = <&audsys CLK_AUD_AFE>,
94                 <&audsys CLK_AUD_DAC>,
95                 <&audsys CLK_AUD_DAC_PREDIS>,
96                 <&infracfg CLK_INFRA_AUDIO>,
97                 <&infracfg CLK_INFRA_AUDIO_26M_B>;
98        clock-names = "aud_afe_clk",
99                      "aud_dac_clk",
100                      "aud_dac_predis_clk",
101                      "aud_infra_clk",
102                      "aud_infra_26m_clk";
103    };
104
105...
106