1Mediatek AFE PCM controller for mt2701
2
3Required properties:
4- compatible = "mediatek,mt2701-audio";
5- reg: register location and size
6- interrupts: should contain AFE and ASYS interrupts
7- interrupt-names: should be "afe" and "asys"
8- power-domains: should define the power domain
9- clock-names: should have these clock names:
10		"infra_sys_audio_clk",
11		"top_audio_mux1_sel",
12		"top_audio_mux2_sel",
13		"top_audio_mux1_div",
14		"top_audio_mux2_div",
15		"top_audio_48k_timing",
16		"top_audio_44k_timing",
17		"top_audpll_mux_sel",
18		"top_apll_sel",
19		"top_aud1_pll_98M",
20		"top_aud2_pll_90M",
21		"top_hadds2_pll_98M",
22		"top_hadds2_pll_294M",
23		"top_audpll",
24		"top_audpll_d4",
25		"top_audpll_d8",
26		"top_audpll_d16",
27		"top_audpll_d24",
28		"top_audintbus_sel",
29		"clk_26m",
30		"top_syspll1_d4",
31		"top_aud_k1_src_sel",
32		"top_aud_k2_src_sel",
33		"top_aud_k3_src_sel",
34		"top_aud_k4_src_sel",
35		"top_aud_k5_src_sel",
36		"top_aud_k6_src_sel",
37		"top_aud_k1_src_div",
38		"top_aud_k2_src_div",
39		"top_aud_k3_src_div",
40		"top_aud_k4_src_div",
41		"top_aud_k5_src_div",
42		"top_aud_k6_src_div",
43		"top_aud_i2s1_mclk",
44		"top_aud_i2s2_mclk",
45		"top_aud_i2s3_mclk",
46		"top_aud_i2s4_mclk",
47		"top_aud_i2s5_mclk",
48		"top_aud_i2s6_mclk",
49		"top_asm_m_sel",
50		"top_asm_h_sel",
51		"top_univpll2_d4",
52		"top_univpll2_d2",
53		"top_syspll_d5";
54
55Example:
56
57	afe: mt2701-afe-pcm@11220000 {
58		compatible = "mediatek,mt2701-audio";
59		reg = <0 0x11220000 0 0x2000>,
60		      <0 0x112A0000 0 0x20000>;
61		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
62			     <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
63		interrupt-names	= "afe", "asys";
64		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
65		clocks = <&infracfg CLK_INFRA_AUDIO>,
66			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
67			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
68			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
69			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
70			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
71			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
72			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
73			 <&topckgen CLK_TOP_APLL_SEL>,
74			 <&topckgen CLK_TOP_AUD1PLL_98M>,
75			 <&topckgen CLK_TOP_AUD2PLL_90M>,
76			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
77			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
78			 <&topckgen CLK_TOP_AUDPLL>,
79			 <&topckgen CLK_TOP_AUDPLL_D4>,
80			 <&topckgen CLK_TOP_AUDPLL_D8>,
81			 <&topckgen CLK_TOP_AUDPLL_D16>,
82			 <&topckgen CLK_TOP_AUDPLL_D24>,
83			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
84			 <&clk26m>,
85			 <&topckgen CLK_TOP_SYSPLL1_D4>,
86			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
87			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
88			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
89			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
90			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
91			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
92			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
93			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
94			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
95			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
96			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
97			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
98			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
99			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
100			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
101			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
102			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
103			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
104			 <&topckgen CLK_TOP_ASM_M_SEL>,
105			 <&topckgen CLK_TOP_ASM_H_SEL>,
106			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
107			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
108			 <&topckgen CLK_TOP_SYSPLL_D5>;
109
110		clock-names = "infra_sys_audio_clk",
111			      "top_audio_mux1_sel",
112			      "top_audio_mux2_sel",
113			      "top_audio_mux1_div",
114			      "top_audio_mux2_div",
115			      "top_audio_48k_timing",
116			      "top_audio_44k_timing",
117			      "top_audpll_mux_sel",
118			      "top_apll_sel",
119			      "top_aud1_pll_98M",
120			      "top_aud2_pll_90M",
121			      "top_hadds2_pll_98M",
122			      "top_hadds2_pll_294M",
123			      "top_audpll",
124			      "top_audpll_d4",
125			      "top_audpll_d8",
126			      "top_audpll_d16",
127			      "top_audpll_d24",
128			      "top_audintbus_sel",
129			      "clk_26m",
130			      "top_syspll1_d4",
131			      "top_aud_k1_src_sel",
132			      "top_aud_k2_src_sel",
133			      "top_aud_k3_src_sel",
134			      "top_aud_k4_src_sel",
135			      "top_aud_k5_src_sel",
136			      "top_aud_k6_src_sel",
137			      "top_aud_k1_src_div",
138			      "top_aud_k2_src_div",
139			      "top_aud_k3_src_div",
140			      "top_aud_k4_src_div",
141			      "top_aud_k5_src_div",
142			      "top_aud_k6_src_div",
143			      "top_aud_i2s1_mclk",
144			      "top_aud_i2s2_mclk",
145			      "top_aud_i2s3_mclk",
146			      "top_aud_i2s4_mclk",
147			      "top_aud_i2s5_mclk",
148			      "top_aud_i2s6_mclk",
149			      "top_asm_m_sel",
150			      "top_asm_h_sel",
151			      "top_univpll2_d4",
152			      "top_univpll2_d2",
153			      "top_syspll_d5";
154	};
155