1Mediatek AFE PCM controller for mt2701
2
3Required properties:
4- compatible = "mediatek,mt2701-audio";
5- reg: register location and size
6- interrupts: Should contain AFE interrupt
7- power-domains: should define the power domain
8- clock-names: should have these clock names:
9		"infra_sys_audio_clk",
10		"top_audio_mux1_sel",
11		"top_audio_mux2_sel",
12		"top_audio_mux1_div",
13		"top_audio_mux2_div",
14		"top_audio_48k_timing",
15		"top_audio_44k_timing",
16		"top_audpll_mux_sel",
17		"top_apll_sel",
18		"top_aud1_pll_98M",
19		"top_aud2_pll_90M",
20		"top_hadds2_pll_98M",
21		"top_hadds2_pll_294M",
22		"top_audpll",
23		"top_audpll_d4",
24		"top_audpll_d8",
25		"top_audpll_d16",
26		"top_audpll_d24",
27		"top_audintbus_sel",
28		"clk_26m",
29		"top_syspll1_d4",
30		"top_aud_k1_src_sel",
31		"top_aud_k2_src_sel",
32		"top_aud_k3_src_sel",
33		"top_aud_k4_src_sel",
34		"top_aud_k5_src_sel",
35		"top_aud_k6_src_sel",
36		"top_aud_k1_src_div",
37		"top_aud_k2_src_div",
38		"top_aud_k3_src_div",
39		"top_aud_k4_src_div",
40		"top_aud_k5_src_div",
41		"top_aud_k6_src_div",
42		"top_aud_i2s1_mclk",
43		"top_aud_i2s2_mclk",
44		"top_aud_i2s3_mclk",
45		"top_aud_i2s4_mclk",
46		"top_aud_i2s5_mclk",
47		"top_aud_i2s6_mclk",
48		"top_asm_m_sel",
49		"top_asm_h_sel",
50		"top_univpll2_d4",
51		"top_univpll2_d2",
52		"top_syspll_d5";
53
54Example:
55
56	afe: mt2701-afe-pcm@11220000 {
57		compatible = "mediatek,mt2701-audio";
58		reg = <0 0x11220000 0 0x2000>,
59		      <0 0x112A0000 0 0x20000>;
60		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
61			     <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
62		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
63		clocks = <&infracfg CLK_INFRA_AUDIO>,
64			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
65			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
66			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
67			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
68			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
69			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
70			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
71			 <&topckgen CLK_TOP_APLL_SEL>,
72			 <&topckgen CLK_TOP_AUD1PLL_98M>,
73			 <&topckgen CLK_TOP_AUD2PLL_90M>,
74			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
75			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
76			 <&topckgen CLK_TOP_AUDPLL>,
77			 <&topckgen CLK_TOP_AUDPLL_D4>,
78			 <&topckgen CLK_TOP_AUDPLL_D8>,
79			 <&topckgen CLK_TOP_AUDPLL_D16>,
80			 <&topckgen CLK_TOP_AUDPLL_D24>,
81			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
82			 <&clk26m>,
83			 <&topckgen CLK_TOP_SYSPLL1_D4>,
84			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
85			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
86			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
87			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
88			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
89			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
90			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
91			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
92			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
93			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
94			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
95			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
96			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
97			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
98			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
99			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
100			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
101			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
102			 <&topckgen CLK_TOP_ASM_M_SEL>,
103			 <&topckgen CLK_TOP_ASM_H_SEL>,
104			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
105			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
106			 <&topckgen CLK_TOP_SYSPLL_D5>;
107
108		clock-names = "infra_sys_audio_clk",
109			      "top_audio_mux1_sel",
110			      "top_audio_mux2_sel",
111			      "top_audio_mux1_div",
112			      "top_audio_mux2_div",
113			      "top_audio_48k_timing",
114			      "top_audio_44k_timing",
115			      "top_audpll_mux_sel",
116			      "top_apll_sel",
117			      "top_aud1_pll_98M",
118			      "top_aud2_pll_90M",
119			      "top_hadds2_pll_98M",
120			      "top_hadds2_pll_294M",
121			      "top_audpll",
122			      "top_audpll_d4",
123			      "top_audpll_d8",
124			      "top_audpll_d16",
125			      "top_audpll_d24",
126			      "top_audintbus_sel",
127			      "clk_26m",
128			      "top_syspll1_d4",
129			      "top_aud_k1_src_sel",
130			      "top_aud_k2_src_sel",
131			      "top_aud_k3_src_sel",
132			      "top_aud_k4_src_sel",
133			      "top_aud_k5_src_sel",
134			      "top_aud_k6_src_sel",
135			      "top_aud_k1_src_div",
136			      "top_aud_k2_src_div",
137			      "top_aud_k3_src_div",
138			      "top_aud_k4_src_div",
139			      "top_aud_k5_src_div",
140			      "top_aud_k6_src_div",
141			      "top_aud_i2s1_mclk",
142			      "top_aud_i2s2_mclk",
143			      "top_aud_i2s3_mclk",
144			      "top_aud_i2s4_mclk",
145			      "top_aud_i2s5_mclk",
146			      "top_aud_i2s6_mclk",
147			      "top_asm_m_sel",
148			      "top_asm_h_sel",
149			      "top_univpll2_d4",
150			      "top_univpll2_d2",
151			      "top_syspll_d5";
152	};
153