1Mediatek AFE PCM controller for mt2701
2
3Required properties:
4- compatible = "mediatek,mt2701-audio";
5- interrupts: should contain AFE and ASYS interrupts
6- interrupt-names: should be "afe" and "asys"
7- power-domains: should define the power domain
8- clocks: Must contain an entry for each entry in clock-names
9  See ../clocks/clock-bindings.txt for details
10- clock-names: should have these clock names:
11		"infra_sys_audio_clk",
12		"top_audio_mux1_sel",
13		"top_audio_mux2_sel",
14		"top_audio_a1sys_hp",
15		"top_audio_a2sys_hp",
16		"i2s0_src_sel",
17		"i2s1_src_sel",
18		"i2s2_src_sel",
19		"i2s3_src_sel",
20		"i2s0_src_div",
21		"i2s1_src_div",
22		"i2s2_src_div",
23		"i2s3_src_div",
24		"i2s0_mclk_en",
25		"i2s1_mclk_en",
26		"i2s2_mclk_en",
27		"i2s3_mclk_en",
28		"i2so0_hop_ck",
29		"i2so1_hop_ck",
30		"i2so2_hop_ck",
31		"i2so3_hop_ck",
32		"i2si0_hop_ck",
33		"i2si1_hop_ck",
34		"i2si2_hop_ck",
35		"i2si3_hop_ck",
36		"asrc0_out_ck",
37		"asrc1_out_ck",
38		"asrc2_out_ck",
39		"asrc3_out_ck",
40		"audio_afe_pd",
41		"audio_afe_conn_pd",
42		"audio_a1sys_pd",
43		"audio_a2sys_pd",
44		"audio_mrgif_pd";
45- assigned-clocks: list of input clocks and dividers for the audio system.
46		   See ../clocks/clock-bindings.txt for details.
47- assigned-clocks-parents: parent of input clocks of assigned clocks.
48- assigned-clock-rates: list of clock frequencies of assigned clocks.
49
50Must be a subnode of MediaTek audsys device tree node.
51See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
52
53Example:
54
55	audsys: audio-subsystem@11220000 {
56		compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
57		...
58
59		afe: audio-controller {
60			compatible = "mediatek,mt2701-audio";
61			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
62				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
63			interrupt-names	= "afe", "asys";
64			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
65
66			clocks = <&infracfg CLK_INFRA_AUDIO>,
67				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
68				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
69				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
70				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
71				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
72				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
73				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
74				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
75				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
76				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
77				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
78				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
79				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
80				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
81				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
82				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
83				 <&audsys CLK_AUD_I2SO1>,
84				 <&audsys CLK_AUD_I2SO2>,
85				 <&audsys CLK_AUD_I2SO3>,
86				 <&audsys CLK_AUD_I2SO4>,
87				 <&audsys CLK_AUD_I2SIN1>,
88				 <&audsys CLK_AUD_I2SIN2>,
89				 <&audsys CLK_AUD_I2SIN3>,
90				 <&audsys CLK_AUD_I2SIN4>,
91				 <&audsys CLK_AUD_ASRCO1>,
92				 <&audsys CLK_AUD_ASRCO2>,
93				 <&audsys CLK_AUD_ASRCO3>,
94				 <&audsys CLK_AUD_ASRCO4>,
95				 <&audsys CLK_AUD_AFE>,
96				 <&audsys CLK_AUD_AFE_CONN>,
97				 <&audsys CLK_AUD_A1SYS>,
98				 <&audsys CLK_AUD_A2SYS>,
99				 <&audsys CLK_AUD_AFE_MRGIF>;
100
101			clock-names = "infra_sys_audio_clk",
102				      "top_audio_mux1_sel",
103				      "top_audio_mux2_sel",
104				      "top_audio_a1sys_hp",
105				      "top_audio_a2sys_hp",
106				      "i2s0_src_sel",
107				      "i2s1_src_sel",
108				      "i2s2_src_sel",
109				      "i2s3_src_sel",
110				      "i2s0_src_div",
111				      "i2s1_src_div",
112				      "i2s2_src_div",
113				      "i2s3_src_div",
114				      "i2s0_mclk_en",
115				      "i2s1_mclk_en",
116				      "i2s2_mclk_en",
117				      "i2s3_mclk_en",
118				      "i2so0_hop_ck",
119				      "i2so1_hop_ck",
120				      "i2so2_hop_ck",
121				      "i2so3_hop_ck",
122				      "i2si0_hop_ck",
123				      "i2si1_hop_ck",
124				      "i2si2_hop_ck",
125				      "i2si3_hop_ck",
126				      "asrc0_out_ck",
127				      "asrc1_out_ck",
128				      "asrc2_out_ck",
129				      "asrc3_out_ck",
130				      "audio_afe_pd",
131				      "audio_afe_conn_pd",
132				      "audio_a1sys_pd",
133				      "audio_a2sys_pd",
134				      "audio_mrgif_pd";
135
136			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
137					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
138					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
139					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
140			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
141						 <&topckgen CLK_TOP_AUD2PLL_90M>;
142			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
143		};
144	};
145