1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek AFE PCM controller for mt8188
8
9maintainers:
10  - Trevor Wu <trevor.wu@mediatek.com>
11
12properties:
13  compatible:
14    const: mediatek,mt8188-afe
15
16  reg:
17    maxItems: 1
18
19  interrupts:
20    maxItems: 1
21
22  resets:
23    maxItems: 1
24
25  reset-names:
26    const: audiosys
27
28  mediatek,topckgen:
29    $ref: /schemas/types.yaml#/definitions/phandle
30    description: The phandle of the mediatek topckgen controller
31
32  mediatek,infracfg:
33    $ref: /schemas/types.yaml#/definitions/phandle
34    description: The phandle of the mediatek infracfg controller
35
36  power-domains:
37    maxItems: 1
38
39  clocks:
40    items:
41      - description: 26M clock
42      - description: audio pll1 clock
43      - description: audio pll2 clock
44      - description: clock divider for i2si1_mck
45      - description: clock divider for i2si2_mck
46      - description: clock divider for i2so1_mck
47      - description: clock divider for i2so2_mck
48      - description: clock divider for dptx_mck
49      - description: a1sys hoping clock
50      - description: audio intbus clock
51      - description: audio hires clock
52      - description: audio local bus clock
53      - description: mux for dptx_mck
54      - description: mux for i2so1_mck
55      - description: mux for i2so2_mck
56      - description: mux for i2si1_mck
57      - description: mux for i2si2_mck
58      - description: audio 26m clock
59      - description: audio pll1 divide 4
60      - description: audio pll2 divide 4
61      - description: clock divider for iec
62      - description: mux for a2sys clock
63      - description: mux for aud_iec
64
65  clock-names:
66    items:
67      - const: clk26m
68      - const: apll1
69      - const: apll2
70      - const: apll12_div0
71      - const: apll12_div1
72      - const: apll12_div2
73      - const: apll12_div3
74      - const: apll12_div9
75      - const: top_a1sys_hp
76      - const: top_aud_intbus
77      - const: top_audio_h
78      - const: top_audio_local_bus
79      - const: top_dptx
80      - const: top_i2so1
81      - const: top_i2so2
82      - const: top_i2si1
83      - const: top_i2si2
84      - const: adsp_audio_26m
85      - const: apll1_d4
86      - const: apll2_d4
87      - const: apll12_div4
88      - const: top_a2sys
89      - const: top_aud_iec
90
91  mediatek,etdm-in1-cowork-source:
92    $ref: /schemas/types.yaml#/definitions/uint32
93    description:
94      etdm modules can share the same external clock pin. Specify
95      which etdm clock source is required by this etdm in module.
96    enum:
97      - 1 # etdm2_in
98      - 2 # etdm1_out
99      - 3 # etdm2_out
100
101  mediatek,etdm-in2-cowork-source:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      etdm modules can share the same external clock pin. Specify
105      which etdm clock source is required by this etdm in module.
106    enum:
107      - 0 # etdm1_in
108      - 2 # etdm1_out
109      - 3 # etdm2_out
110
111  mediatek,etdm-out1-cowork-source:
112    $ref: /schemas/types.yaml#/definitions/uint32
113    description:
114      etdm modules can share the same external clock pin. Specify
115      which etdm clock source is required by this etdm out module.
116    enum:
117      - 0 # etdm1_in
118      - 1 # etdm2_in
119      - 3 # etdm2_out
120
121  mediatek,etdm-out2-cowork-source:
122    $ref: /schemas/types.yaml#/definitions/uint32
123    description:
124      etdm modules can share the same external clock pin. Specify
125      which etdm clock source is required by this etdm out module.
126    enum:
127      - 0 # etdm1_in
128      - 1 # etdm2_in
129      - 2 # etdm1_out
130
131patternProperties:
132  "^mediatek,etdm-in[1-2]-chn-disabled$":
133    $ref: /schemas/types.yaml#/definitions/uint8-array
134    minItems: 1
135    maxItems: 16
136    description:
137      This is a list of channel IDs which should be disabled.
138      By default, all data received from ETDM pins will be outputed to
139      memory. etdm in supports disable_out in direct mode(w/o interconn),
140      so user can disable the specified channels by the property.
141    uniqueItems: true
142    items:
143      minimum: 0
144      maximum: 15
145
146  "^mediatek,etdm-in[1-2]-multi-pin-mode$":
147    type: boolean
148    description: if present, the etdm data mode is I2S.
149
150  "^mediatek,etdm-out[1-3]-multi-pin-mode$":
151    type: boolean
152    description: if present, the etdm data mode is I2S.
153
154required:
155  - compatible
156  - reg
157  - interrupts
158  - resets
159  - reset-names
160  - mediatek,topckgen
161  - mediatek,infracfg
162  - power-domains
163  - clocks
164  - clock-names
165
166additionalProperties: false
167
168examples:
169  - |
170    #include <dt-bindings/interrupt-controller/arm-gic.h>
171    #include <dt-bindings/interrupt-controller/irq.h>
172
173    afe@10b10000 {
174        compatible = "mediatek,mt8188-afe";
175        reg = <0x10b10000 0x10000>;
176        interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
177        resets = <&watchdog 14>;
178        reset-names = "audiosys";
179        mediatek,topckgen = <&topckgen>;
180        mediatek,infracfg = <&infracfg_ao>;
181        power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO
182        mediatek,etdm-in2-cowork-source = <2>;
183        mediatek,etdm-out2-cowork-source = <0>;
184        mediatek,etdm-in1-multi-pin-mode;
185        mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>;
186        clocks = <&clk26m>,
187                 <&apmixedsys 9>, //CLK_APMIXED_APLL1
188                 <&apmixedsys 10>, //CLK_APMIXED_APLL2
189                 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
190                 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
191                 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
192                 <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
193                 <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
194                 <&topckgen 83>, //CLK_TOP_A1SYS_HP
195                 <&topckgen 31>, //CLK_TOP_AUD_INTBUS
196                 <&topckgen 32>, //CLK_TOP_AUDIO_H
197                 <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS
198                 <&topckgen 81>, //CLK_TOP_DPTX
199                 <&topckgen 77>, //CLK_TOP_I2SO1
200                 <&topckgen 78>, //CLK_TOP_I2SO2
201                 <&topckgen 79>, //CLK_TOP_I2SI1
202                 <&topckgen 80>, //CLK_TOP_I2SI2
203                 <&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M
204                 <&topckgen 132>, //CLK_TOP_APLL1_D4
205                 <&topckgen 133>, //CLK_TOP_APLL2_D4
206                 <&topckgen 183>, //CLK_TOP_APLL12_CK_DIV4
207                 <&topckgen 84>, //CLK_TOP_A2SYS
208                 <&topckgen 82>; //CLK_TOP_AUD_IEC>;
209        clock-names = "clk26m",
210                      "apll1",
211                      "apll2",
212                      "apll12_div0",
213                      "apll12_div1",
214                      "apll12_div2",
215                      "apll12_div3",
216                      "apll12_div9",
217                      "top_a1sys_hp",
218                      "top_aud_intbus",
219                      "top_audio_h",
220                      "top_audio_local_bus",
221                      "top_dptx",
222                      "top_i2so1",
223                      "top_i2so2",
224                      "top_i2si1",
225                      "top_i2si2",
226                      "adsp_audio_26m",
227                      "apll1_d4",
228                      "apll2_d4",
229                      "apll12_div4",
230                      "top_a2sys",
231                      "top_aud_iec";
232    };
233
234...
235