1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Synchronous Audio Interface (SAI).
8
9maintainers:
10  - Shengjiu Wang <shengjiu.wang@nxp.com>
11
12description: |
13  The SAI is based on I2S module that used communicating with audio codecs,
14  which provides a synchronous audio interface that supports fullduplex
15  serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16  codec/DSP interfaces.
17
18properties:
19  compatible:
20    oneOf:
21      - enum:
22          - fsl,vf610-sai
23          - fsl,imx6sx-sai
24          - fsl,imx6ul-sai
25          - fsl,imx7ulp-sai
26          - fsl,imx8mq-sai
27          - fsl,imx8qm-sai
28          - fsl,imx8ulp-sai
29      - items:
30          - enum:
31              - fsl,imx8mm-sai
32              - fsl,imx8mn-sai
33              - fsl,imx8mp-sai
34          - const: fsl,imx8mq-sai
35
36  reg:
37    maxItems: 1
38
39  interrupts:
40    items:
41      - description: receive and transmit interrupt
42
43  dmas:
44    maxItems: 2
45
46  dma-names:
47    maxItems: 2
48
49  clocks:
50    items:
51      - description: The ipg clock for register access
52      - description: master clock source 0 (obsoleted)
53      - description: master clock source 1
54      - description: master clock source 2
55      - description: master clock source 3
56      - description: PLL clock source for 8kHz series
57      - description: PLL clock source for 11kHz series
58    minItems: 4
59
60  clock-names:
61    oneOf:
62      - items:
63          - const: bus
64          - const: mclk0
65          - const: mclk1
66          - const: mclk2
67          - const: mclk3
68          - const: pll8k
69          - const: pll11k
70        minItems: 4
71      - items:
72          - const: bus
73          - const: mclk1
74          - const: mclk2
75          - const: mclk3
76          - const: pll8k
77          - const: pll11k
78        minItems: 4
79
80  lsb-first:
81    description: |
82      Configures whether the LSB or the MSB is transmitted
83      first for the fifo data. If this property is absent,
84      the MSB is transmitted first as default, or the LSB
85      is transmitted first.
86    type: boolean
87
88  big-endian:
89    description: |
90      required if all the SAI registers are big-endian rather than little-endian.
91    type: boolean
92
93  fsl,sai-synchronous-rx:
94    description: |
95      SAI will work in the synchronous mode (sync Tx with Rx) which means
96      both the transmitter and the receiver will send and receive data by
97      following receiver's bit clocks and frame sync clocks.
98    type: boolean
99
100  fsl,sai-asynchronous:
101    description: |
102      SAI will work in the asynchronous mode, which means both transmitter
103      and receiver will send and receive data by following their own bit clocks
104      and frame sync clocks separately.
105      If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
106      default synchronous mode (sync Rx with Tx) will be used, which means both
107      transmitter and receiver will send and receive data by following clocks
108      of transmitter.
109    type: boolean
110
111  fsl,dataline:
112    $ref: /schemas/types.yaml#/definitions/uint32-matrix
113    description: |
114      Configure the dataline. It has 3 value for each configuration
115    maxItems: 16
116    items:
117      items:
118        - description: format Default(0), I2S(1) or PDM(2)
119          enum: [0, 1, 2]
120        - description: dataline mask for 'rx'
121        - description: dataline mask for 'tx'
122
123  fsl,sai-mclk-direction-output:
124    description: SAI will output the SAI MCLK clock.
125    type: boolean
126
127  fsl,shared-interrupt:
128    description: Interrupt is shared with other modules.
129    type: boolean
130
131  "#sound-dai-cells":
132    const: 0
133    description: optional, some dts node didn't add it.
134
135allOf:
136  - if:
137      properties:
138        compatible:
139          contains:
140            const: fsl,vf610-sai
141    then:
142      properties:
143        dmas:
144          items:
145            - description: DMA controller phandle and request line for TX
146            - description: DMA controller phandle and request line for RX
147        dma-names:
148          items:
149            - const: tx
150            - const: rx
151    else:
152      properties:
153        dmas:
154          items:
155            - description: DMA controller phandle and request line for RX
156            - description: DMA controller phandle and request line for TX
157        dma-names:
158          items:
159            - const: rx
160            - const: tx
161  - if:
162      required:
163        - fsl,sai-asynchronous
164    then:
165      properties:
166        fsl,sai-synchronous-rx: false
167
168required:
169  - compatible
170  - reg
171  - interrupts
172  - dmas
173  - dma-names
174  - clocks
175  - clock-names
176
177additionalProperties: false
178
179examples:
180  - |
181    #include <dt-bindings/interrupt-controller/arm-gic.h>
182    #include <dt-bindings/clock/vf610-clock.h>
183    sai2: sai@40031000 {
184        compatible = "fsl,vf610-sai";
185        reg = <0x40031000 0x1000>;
186        interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
187        pinctrl-names = "default";
188        pinctrl-0 = <&pinctrl_sai2_1>;
189        clocks = <&clks VF610_CLK_PLATFORM_BUS>,
190                 <&clks VF610_CLK_SAI2>,
191                 <&clks 0>, <&clks 0>;
192        clock-names = "bus", "mclk1", "mclk2", "mclk3";
193        dma-names = "tx", "rx";
194        dmas = <&edma0 0 21>,
195               <&edma0 0 20>;
196        big-endian;
197        lsb-first;
198    };
199
200  - |
201    #include <dt-bindings/interrupt-controller/arm-gic.h>
202    #include <dt-bindings/clock/imx8mm-clock.h>
203    sai1: sai@30010000 {
204        compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
205        reg = <0x30010000 0x10000>;
206        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
207        clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
208                 <&clk IMX8MM_CLK_DUMMY>,
209                 <&clk IMX8MM_CLK_SAI1_ROOT>,
210                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
211        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
212        dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
213        dma-names = "rx", "tx";
214        fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
215        #sound-dai-cells = <0>;
216    };
217