1*6f786754SRyan Wanner# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*6f786754SRyan Wanner# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3*6f786754SRyan Wanner%YAML 1.2
4*6f786754SRyan Wanner---
5*6f786754SRyan Wanner$id: http://devicetree.org/schemas/sound/atmel,sama5d2-i2s.yaml#
6*6f786754SRyan Wanner$schema: http://devicetree.org/meta-schemas/core.yaml#
7*6f786754SRyan Wanner
8*6f786754SRyan Wannertitle: Atmel I2S controller
9*6f786754SRyan Wanner
10*6f786754SRyan Wannermaintainers:
11*6f786754SRyan Wanner  - Nicolas Ferre <nicolas.ferre@microchip.com>
12*6f786754SRyan Wanner  - Alexandre Belloni <alexandre.belloni@bootlin.com>
13*6f786754SRyan Wanner  - Claudiu Beznea <claudiu.beznea@microchip.com>
14*6f786754SRyan Wanner
15*6f786754SRyan Wannerdescription:
16*6f786754SRyan Wanner  Atmel I2S (Inter-IC Sound Controller) bus is the standard
17*6f786754SRyan Wanner  interface for connecting audio devices, such as audio codecs.
18*6f786754SRyan Wanner
19*6f786754SRyan Wannerproperties:
20*6f786754SRyan Wanner  compatible:
21*6f786754SRyan Wanner    const: atmel,sama5d2-i2s
22*6f786754SRyan Wanner
23*6f786754SRyan Wanner  reg:
24*6f786754SRyan Wanner    maxItems: 1
25*6f786754SRyan Wanner
26*6f786754SRyan Wanner  interrupts:
27*6f786754SRyan Wanner    maxItems: 1
28*6f786754SRyan Wanner
29*6f786754SRyan Wanner  clocks:
30*6f786754SRyan Wanner    items:
31*6f786754SRyan Wanner      - description: Peripheral clock
32*6f786754SRyan Wanner      - description: Generated clock (Optional)
33*6f786754SRyan Wanner      - description: I2S mux clock (Optional). Set
34*6f786754SRyan Wanner          with gclk when Master Mode is required.
35*6f786754SRyan Wanner    minItems: 1
36*6f786754SRyan Wanner
37*6f786754SRyan Wanner  clock-names:
38*6f786754SRyan Wanner    items:
39*6f786754SRyan Wanner      - const: pclk
40*6f786754SRyan Wanner      - const: gclk
41*6f786754SRyan Wanner      - const: muxclk
42*6f786754SRyan Wanner    minItems: 1
43*6f786754SRyan Wanner
44*6f786754SRyan Wanner  dmas:
45*6f786754SRyan Wanner    items:
46*6f786754SRyan Wanner      - description: TX DMA Channel
47*6f786754SRyan Wanner      - description: RX DMA Channel
48*6f786754SRyan Wanner
49*6f786754SRyan Wanner  dma-names:
50*6f786754SRyan Wanner    items:
51*6f786754SRyan Wanner      - const: tx
52*6f786754SRyan Wanner      - const: rx
53*6f786754SRyan Wanner
54*6f786754SRyan Wannerrequired:
55*6f786754SRyan Wanner  - compatible
56*6f786754SRyan Wanner  - reg
57*6f786754SRyan Wanner  - interrupts
58*6f786754SRyan Wanner  - dmas
59*6f786754SRyan Wanner  - dma-names
60*6f786754SRyan Wanner  - clocks
61*6f786754SRyan Wanner  - clock-names
62*6f786754SRyan Wanner
63*6f786754SRyan WanneradditionalProperties: false
64*6f786754SRyan Wanner
65*6f786754SRyan Wannerexamples:
66*6f786754SRyan Wanner  - |
67*6f786754SRyan Wanner    #include <dt-bindings/dma/at91.h>
68*6f786754SRyan Wanner    #include <dt-bindings/interrupt-controller/arm-gic.h>
69*6f786754SRyan Wanner
70*6f786754SRyan Wanner    i2s@f8050000 {
71*6f786754SRyan Wanner        compatible = "atmel,sama5d2-i2s";
72*6f786754SRyan Wanner        reg = <0xf8050000 0x300>;
73*6f786754SRyan Wanner        interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
74*6f786754SRyan Wanner        dmas = <&dma0
75*6f786754SRyan Wanner                (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
76*6f786754SRyan Wanner                AT91_XDMAC_DT_PERID(31))>,
77*6f786754SRyan Wanner               <&dma0
78*6f786754SRyan Wanner                (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
79*6f786754SRyan Wanner                AT91_XDMAC_DT_PERID(32))>;
80*6f786754SRyan Wanner        dma-names = "tx", "rx";
81*6f786754SRyan Wanner        clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>;
82*6f786754SRyan Wanner        clock-names = "pclk", "gclk", "muxclk";
83*6f786754SRyan Wanner        pinctrl-names = "default";
84*6f786754SRyan Wanner        pinctrl-0 = <&pinctrl_i2s0_default>;
85*6f786754SRyan Wanner    };
86